The 1800 LRM says, "A mechanism is included for specifying properties about objects, statements, and groups of statements in the SystemVerilog source that can be used by various tools, including simulators, to control the operation or behavior of the tool." The V-AMS LRM says, "With the proliferation of tools other than simulators that use Verilog-AMS HDL as their source, a mechanism is included for specifying properties about objects, statements and groups of statements in the HDL source that can be used by various tools, including simulators, to control the operation or behavior of the tool." > A slightly different question on attributes - Attributes as i > understand are hints to the simulator ie. do not change the > behavior or the results. Is this always true? So an attribute could be defined that would change simulator behavior. Shalom --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jul 3 01:47:19 2008
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