Re: reducing warning messages

Wow ... I'd had the impression that I'd read somewhere that attributes
were not allowed to change the results of a simulation -- that they
were hints that might allow a simulator to work more efficiently.
I also had the impression that simulators were supposed to ignore
attributes that they didn't recognize.  But none of this is in the
LRM text that Shalom cited.

-Geoffrey


Bresticker, Shalom wrote:
> I don't think that there is anything that says that you cannot define a
> standard attribute in the standard that a simulator must support in
> order to be called conformant with the standard.
> 
> Shalom 
> 
>> -----Original Message-----
>> From: Sri Chandra [mailto:sri.chandra@freescale.com] 
>> Sent: Thursday, July 03, 2008 11:58 AM
>> To: Bresticker, Shalom
>> Cc: Geoffrey.Coram; VerilogAMS Reflector
>> Subject: Re: reducing warning messages
>>
>> Yeah, I understand today we have the scenario that attributes 
>> change the behavior of the tool, but some of them (I feel) 
>> should be ideally part of the language. Of course its very 
>> difficult to look at various implementations/attributes and 
>> correctly understand the intent behind these attributes.
>>
>> I hope some of the more key features (if any) implemented 
>> through attributes because of lack of support through the 
>> language provided by various simulator tools are discussed 
>> and made part of the standard to make the models 
>> inter-operable and standardize the language.
>>
>> Of course, this point has been discussed a few times in the 
>> past through the committee discussions and we have put some 
>> notes saying attributes may not be compatible.
>>
>> Regards,
>> Sri
>>
>> Bresticker, Shalom wrote:
>>> The 1800 LRM says,
>>>
>>> "A mechanism is included for specifying properties about objects, 
>>> statements, and groups of statements in the SystemVerilog 
>> source that 
>>> can be used by various tools, including simulators, to control the 
>>> operation or behavior of the tool."
>>>
>>> The V-AMS LRM says,
>>>
>>> "With the proliferation of tools other than simulators that use 
>>> Verilog-AMS HDL as their source, a mechanism is included for 
>>> specifying properties about objects, statements and groups of 
>>> statements in the HDL source that can be used by various tools, 
>>> including simulators, to control the operation or behavior 
>> of the tool."
>>>> A slightly different question on attributes - Attributes as i 
>>>> understand are hints to the simulator ie. do not change 
>> the behavior 
>>>> or the results. Is this always true?
>>> So an attribute could be defined that would change 
>> simulator behavior.
>>> Shalom
>>>

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