Hi all, This language only includes the comments submitted to the board as part of the Accellera review process, that was discussed and minuted in the committee meeting on 10th July. The minutes were posted under the subject "Minutes of the Verilog-AMS meeting: 10th July 2008" to the reflector on 11th July (India time). Dave, Thanks for your effort in editing this version and able to post it out very quickly. Appreciate it. Regards, Sri David Miller wrote: > Hello all, > I have updated and post the 2.3/Draft5 version of the LRM: > > http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/VAMS_v2.3-Draft5.pdf > > > We will review this changes on Thursday. The change bars reflect the > modifications I did for *this* draft only. > > Regards > Dave -- Srikanth Chandrasekaran Design Technology (Tools Development) Freescale Semiconductor Inc. T:+91-120-439 5000 p:x3824 f: x5199 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 22 20:39:59 2008
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