Fw: SystemVerilog Assertions and Verilog-AMS

Forwarding a bounced message.

The attachment referenced can be found at

http://www.eda.org/verilog-ams/htmlpages/public-docs/AnalogAssertions_AccelleraProposal_2008_08_12.pdf

-Geoffrey


-------- Original Message --------
When: Tuesday, August 19, 2008 8:30 PM-9:30 PM (GMT+05:30) Chennai, Kolkata=
, Mumbai, New Delhi.
Where: CR-TX32-Bridgepoint-10-BOOK AS RESOURCE

*~*~*~*~*~*~*~*~*~*


Hi all,

There has been some discussions and requests from the community also to ext=
end the SystemVerilog assertions language to AMS. Apart from P1800 integrat=
ion of the main committee and the mixed signal enhancements that Marq is dr=
iving, there is a plan to look at assertions syntax also as a parallel thre=
ad.

As part of that a meeting is planned for next Wednesday, please find the de=
tails of the dial in number and attached initial proposal for analog assert=
ions at the bottom of the email.

Regards,
Sri

> _____________________________________________
> From: 	Anand Himyanshu=20=20
> Sent:	Wednesday, August 13, 2008 09:49
> To:	=3DSMTP:HIMYANSHU.ANAND@freescale.com
> Subject:	Analog-SVA : Dial In: 1848720
> When:	Tuesday, August 19, 2008 8:30 PM-9:30 PM (GMT+05:30) Chennai, Kolka=
ta, Mumbai, New Delhi.
> Where:	CR-TX32-Bridgepoint-10-BOOK AS RESOURCE
>=20
> Sri: Please send this out to Verilog-AMS committee mailing list.
>=20
> Agenda:
>=20
> 1) Introduce our University partners.
> 2) Discuss possible donations and the procedures to be followed for the s=
ame.
> 3) Infrastructure for sub-committee work. (Website, email list, document =
repository,future meeting time, etc.)
> 4) Time permitting - Discuss the first draftof the proposal attached to t=
he meeting notice.
>=20
>  <<AnalogAssertions_AccelleraProposal_2008_08_12.pdf>>=20
>=20
> Dial In Access Code: 1848720
> USA: +1-800-867-1147
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