Analog System Verilog Assertions: Discussion on Time Semantics

From: Anand Himyanshu <HIMYANSHU.ANAND_at_.....>
Date: Wed Aug 20 2008 - 10:19:13 PDT
When: Tuesday, September 23, 2008 11:30 AM-12:30 PM (GMT-06:00) Central Time (US & Canada).
Where: Dial In: Access Code 1848720

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Time: 11:30 AM - 12:30 PM Central Standard Time (Austin Time)

Agenda:

1) Problem scope and definition of Analog System Verilog Assertions (ASVA)
2) Use Cases and Motivating Examples. (I will provide some examples, and would urge other participants too also contribute to motivating examples)
3) Discussion on dense time Vs continuous time Vs simulation time in analog assertion context.

Please go through the links that Dejan has sent so that we can a meaningful discussion. Those of you who are not on the verilog-ams reflector, please follow the instructions given below to get yourself added to the mailing list.

- To subscribe to the committee's e-mail reflector, send an e-mail to majordomo@verilog.org <mailto:majordomo@verilog.org?body=subscribe%20verilog-ams>  with the contents "subscribe verilog-ams".
- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Geoffery Coram has placed the document that was sent with the previous meeting invite at http://www.eda.org/verilog-ams/htmlpages/public-docs/AnalogAssertions_AccelleraProposal_2008_08_12.pdf 
- If you need an account on eda.org please send a mail to Sri.Chandra@freescale.com 
- This is from Dejan: 
----------------------------- 
1) Mostly Event Based: Timed Regular Expressions (version that is defined over dense-time signals) E. Asarin, O. Maler, P. Caspi, Timed Regular Expressions , The Journal of the ACM, 2002. 
http://www-verimag.imag.fr/~maler/Papers/timed.pdf 
2) Original Paper (Signal Based) Timed Regular Expressions (version with real-time events semantics) E. Asarin, O. Maler, P. Caspi, A Kleene Theorem for Timed Automata 
http://www-verimag.imag.fr/PEOPLE/Oded.Maler/Papers/kleene.pdf

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Received on Wed Aug 20 10:19:32 2008

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