Correction: Martin O' Leary (Cadence) also attended the call. In the initial roll call, I had missed his name. Attendees: (Random Order) ----------------------------------------- Verimag: Dejan Nickovic Intel: Erik Seligman, Lertpanyavit Thanapoom Synopsys: Mike Demler, Ed Cerny, Dave Cronauer Mentor Graphics: Dennis B, Kenneth Bakalar Cadence: Martin O' Leary Rambus: Kevin Jones Tiburon Design Automation: Mark Freescale: Sri Chandrasekaran, Scott Little, John Havlicek, Daniel Chrisopher, Saurabh Garg, Benjamin Ehlers, Himyanshu Anand Total Participation: 18 Misc: ------- - Next Meeting on Sept 23rd, 2008, 11:30 am - 12:30 am (CST) - *To subscribe to the committee's e-mail reflector, send an e-mail to majordomo@verilog.org <mailto:majordomo@verilog.org?body=subscribe%20verilog-ams> with the contents "subscribe verilog-ams".* - The current site for verilog-ams is http://eda.org/verilog-ams/ - Geoffery Coram has placed the document that was sent with the meeting invite at http://www.eda.org/verilog-ams/htmlpages/public-docs/AnalogAssertions_AccelleraProposal_2008_08_12.pdf <http://www.eda.org/verilog-ams/htmlpages/public-docs/AnalogAssertions_AccelleraProposal_2008_08_12.pdf> - I (HA) haven't been able to login in to the server (eda.org), will try to resolve it but am going on a long vacation, so in the meantime if you need an account on eda.org please send a mail to Sri.Chandra@freescale.com - This is from Dejan: ----------------------------- 1) Mostly Event Based: Timed Regular Expressions (version that is defined over dense-time signals) E. Asarin, O. Maler, P. Caspi, Timed Regular Expressions , The Journal of the ACM, 2002. http://www-verimag.imag.fr/~maler/Papers/timed.pdf <http://www-verimag.imag.fr/~maler/Papers/timed.pdf> 2) Original Paper (Signal Based) Timed Regular Expressions (version with real-time events semantics) E. Asarin, O. Maler, P. Caspi, A Kleene Theorem for Timed Automata http://www-verimag.imag.fr/PEOPLE/Oded.Maler/Papers/kleene.pdf <http://www-verimag.imag.fr/PEOPLE/Oded.Maler/Papers/kleene.pdf> PS: Please update/correct if I misquoted someone in the minutes below. Sri: - Both the documents (From PSL Work and from IIT Kharagpur) need to be considered for donation to the committee. - Meeting once in about two weeks should be good for start to allow people to go through the documents - Ask Karen Piper for a version of the latest System Verilog LRM, so that the extension work is based on that instead of the old (current) publicly available version. - Setup a reflector with active participants. HA: - For now will use the verilog-ams reflector till the analog sub-committee reflector is setup and login issues are resolved. Will include the instructions to subscribe to verilog-ams reflector in the meeting minutes. - Dejan from Verimag along with Oded Maler and Amir Pnueli have agreed to work with the committee and look into the language semantics and robustness. - Pallab Dasgupta from IIT Kharagpur has also agreed to review the language semantics and provide feedback on the language. Dejan: - The PSL work can be donated to the committee. The thesis will be completed in coming few weeks, then can summarize the relevant portion of the work and donate that to committee. HA: - Any donation should be free of the patents and any other legal rights over the donation by the donating party. The rights are transferred to Accellera after donation. Sri: - Leverage the existing documentation infrastructure of SVA to add/modify/highlight/syntax color coding of the changes that need to be made SVA for Analog extension. Group Discussion: - Merging time (discrete) with Real (continuous) time semantics is difficult and needs to be explored right away before going into details of proposal and syntax issues - Any discussion probably needs a pre-requisite of defining the dense time problem. - We will have to have continuous time semantics - Might need a new syntax to describe the operators and semantics for analog extension - Are we basing the proposal extension on the assumption that the extension will work off the current SVA? We need to look into the requirements first before deciding upon the required extensions. - There is work on Regular Expressions and temporal extensions by Oded, et al. Dejan will send the pointers to the group. - email reflector has some issues, need to resolve that. - Setup the committee reflector and subscribe the attendees to the verilog-ams reflector. Feedback --------------- Intel: ES: Not familiar with Analog requirements LT: Has mixed analog background, some of the stuff is/was(?) considered at Intel. These are the areas which might be beneficial for analog designers. Synopsys: - MD: Analog background. - Need to start from the problem definition. - The analog designs have unique signal behavior. - Need to reach consensus on what assertions need to look like and whether current tool set have overlapping features. EC: Digital background: - Some work was done on extending SVA to real time at system level. - Did not use pre-poned sampling at system level - Event based sampling and was simulation time and not dense time. Dave: No comments Mentor Graphics: BK: Need to look at the requirements before proposing solutions - Tools have measure, extract, post-processing - Utility of extension needs to be measured and debated - First issue is tackling dense time or rather asynchronous time. Does it provide the expressiveness that our customers are asking? Rambus: KJ: Who are the target audience? - Frequency domain like checks (Analog) or Digital Verification/Integrators? - Appropriate semantics need to be defined based on the target audience. - We need to come up with clean examples and test cases (motivating) - Need to first define whether this is targeted at pure analog verification or analog-digital integration boundary crossing errors. - Verilog-AMS was slow - Have papers in DVCon, ICCAD, DAC, etc on the work done by the group. Freescale: JH: Need motivating examples on whether we need continuous temporal logic? - What would regular expression semantics in analog look like? - The latest version is available to the member companies. Others can get it IEEE. - Draft 7.0 of SV will be available in Sept. SL: It looks like the properties in extension would most probably target mixed signal domain. Like crossing the boundary of analog-digital. HA: Will schedule next meeting on Sept 23rd, 11:30 CST (Austin) time. - Agree that all options should be looked at. - Agree that the problem definition needs to be solidified. Will send out pointers to the work being in the area to the group. - Foresee the properties being used at the boundary of analog-digital too. Sri: Will talk to Dr Pallab and get the document describing their work and post it on the website. - Need to have involvement from SVA committee members in order for a successful extension. HA: Yes, we have a good mix of SVA committee members and Verilog-AMS committee members. -Himyanshu. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Aug 22 18:54:41 2008
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