You can see my point-of-view on this topic in my blog posts. The link is below. Regards, Mike "The world is analog" http://synopsysoc.org/analoginsights/ -----Original Appointment----- From: Anand Himyanshu-R61978 [mailto:HIMYANSHU.ANAND@freescale.com] Sent: Monday, September 22, 2008 8:10 PM To: verilog-ams@eda.org; CR-TX32-Great Hills-12-BOOK AS RESOURCE Subject: Updated: Reminder: Analog System Verilog Assertions: Discussion on Time Semantics When: Tuesday, September 23, 2008 9:30 AM-10:30 AM (GMT-08:00) Pacific Time (US & Canada). Where: Dial In: Access Code 1848720 Time: 11:30 AM - 12:30 PM Central Standard Time (Austin Time) (GMT - 5:00) PS: I have added an attachment which we can use to kick start tomorrow's meeting. Thanks to Scott Little, John Havlicek and Hillel Miller for contributing to and reviewing the document. <<AMSproperties.pdf>> Agenda: 1) Problem scope and definition of Analog System Verilog Assertions (ASVA) 2) Use Cases and Motivating Examples. (I will provide some examples, and would urge other participants too also contribute to motivating examples) 3) Discussion on dense time Vs continuous time Vs simulation time in analog assertion context. Please go through the links that Dejan has sent so that we can a meaningful discussion. Those of you who are not on the verilog-ams reflector, please follow the instructions given below to get yourself added to the mailing list. - To subscribe to the committee's e-mail reflector, send an e-mail to majordomo@verilog.org <mailto:majordomo@verilog.org?body=subscribe%20verilog-ams> with the contents "subscribe verilog-ams". - The current site for verilog-ams is http://eda.org/verilog-ams/ - Geoffery Coram has placed the document that was sent with the previous meeting invite at http://www.eda.org/verilog-ams/htmlpages/public-docs/AnalogAssertions_Ac celleraProposal_2008_08_12.pdf - If you need an account on eda.org please send a mail to Sri.Chandra@freescale.com - This is from Dejan: ----------------------------- 1) Mostly Event Based: Timed Regular Expressions (version that is defined over dense-time signals) E. Asarin, O. Maler, P. Caspi, Timed Regular Expressions , The Journal of the ACM, 2002. http://www-verimag.imag.fr/~maler/Papers/timed.pdf 2) Original Paper (Signal Based) Timed Regular Expressions (version with real-time events semantics) E. Asarin, O. Maler, P. Caspi, A Kleene Theorem for Timed Automata http://www-verimag.imag.fr/PEOPLE/Oded.Maler/Papers/kleene.pdf Dial In Access Code: 1848720 USA: +1-800-867-1147 Country Toll free number AUSTRALIA 1800009128 AUSTRIA 0800291873 BELGIUM 080077334 CANADA 8008671147 CHINA TELECOM (CT) 108001201283 CHINA NETCOM (CNC) 108007121283 DENMARK 80703159 FINLAND 0800770233 FRANCE 0800941695 GERMANY 08001014519 GREECE 0080016122039738 HONG KONG 800933578 HUNGARY 0680017180 INDIA 0008001006032 INDONESIA 008800105607 IRELAND 1800944116 ISRAEL 180-945-9738 ITALY 800782388 JAPAN 00531160427 LUXEMBOURG 80023985 MALAYSIA 1800802412 MONACO 80093186 NETHERLANDS 08002658223 NEW ZEALAND 0800443736 NORWAY 80057409 POLAND 008001114672 PORTUGAL 800819106 RUSSIA 81080022801012 SINGAPORE 8001011470 SOUTH AFRICA 0800992835 SOUTH KOREA 00308140540 SPAIN 900967020 SWEDEN 0201400559 SWITZERLAND 0800563054 TAIWAN 00801126585 THAILAND 0018001562039684 UNITED KINGDOM 08005280546 UNITED STATES 8008671147 -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. << File: AMSproperties.pdf >> -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Sep 23 07:33:09 2008
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