Re: Leaky node detection

For the "Power down results in unexpectedly high power consumption" 
problem in Mikes slides, I would suggest having a look at my 
long-standing proposal on power supply connection (and back-annotation):

 http://www.verilog.org/mantis/view.php?id=1754 (guest/guest)
 http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/BackAnnotationProposal

If you can't describe how something is connected you are not going to be 
able to make assertions about the current flow.

The initial motivation for the power-connection proposal was to get A/D 
connection modules tied into the right vdd/vss for for the mixed signal 
boundary, but for a more digital usage it might be worth considering 
adding something like the VHDL "guard" construct where you can gate 
outgoing signals, e.g.:

    module foo(input clock,output out,...)
           parameter standby_current = 1e-10;
           parameter min_working_vdd = 0.5;
    `ifdef SYS_AMS
           default vdd = ^.vdd; // tie power to nearest vdd
           guard (!vdd) begin   // drive outputs to Z if power off
             foo = 1'bz;
           end
           guard (vdd && V(vdd) < min_working_vdd) begin   // drive 
outputs to X if power low
             foo = 1'bx;
           end
    `endif

           // plain old Verilog

           always@(clock)
                out = ...;
           ...

    `ifdef SYS_AMS
           // check for power-off leakage
           analog assert vdd || I(vdd) < standby_current;
    `endif
    endmodule


Feedback appreciated,
Kev.

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