Updated: Analog System Verilog Assertions:

From: Anand Himyanshu-R61978 <HIMYANSHU.ANAND_at_.....>
Date: Thu Oct 16 2008 - 06:45:13 PDT
When: Occurs every 2 weeks on Tuesday effective 10/7/2008 from 11:30 AM to 1:00 PM (GMT-06:00) Central Time (US & Canada).
Where: Dial In Access Code: 1848720

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Time: 11:30 AM - 1:00 PM Central Daylight Time (Austin Time) (GMT - 5:00)

Agenda:

Continuation of discussion on scope. The original idea was to extend SVA with real domain and incorporate the ability to verify analog properties (Safety, Timing and Mixed-Signal properties which are temporal in nature). Previous meetings have explored the expansion of scope which has raised a lot more questions, namely -

a) David Smith asked whether we can have a universal language which can then be mapped to Verilog-AMS, VHDL-AMS and SystemC-AMS.
b) Mike Demler wants to explore electrical property checking mechanism in the language.
c) Ed Cerny presented event based analog extensions to SVA for use across Verilog-AMS to SystemC-AMS
d) Dejan presented STL/PSL work
e) Freescale presented a collection of properties which could be possibly targeted for verification
f) Ken Bakalar wants a discussion on dense time and wants to limit the scope of the current working group.
g) Kevin Cameron wants to review his proposal on power supply connection.
h) David Sharrit raised the question whether this effort would result in a language which would replace the proprietary measurement description languages like MDL, .measure, etc.

We should devote the next meeting to discuss these questions.

- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Till a permanent home is found, documents released to the committee can be found at  http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/

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