Attendees: Listed at the end of the summary Documents: All documents related to Analog assertion released to the committee can be accessed at http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions / <http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertion s/> Summary: (Please correct if I misquoted someone or missed some important point) ------------------------------------------------------------------------ ------------------------------------------------ Discussion on scope of the working group was discussed. There is still not full agreement on the scope, though it was felt by a majority that the scope should be more focused so that problem is practical enough to solve while at the same time interesting enough for not only analog mixed signal designers but also for analog designers. Mike would like to see going beyond the waveform property verification and including more categories from his taxonomy in the assertion language. Ken Bakalar wanted to separate the implementation details from the language definition, as to whether the assertion would be evaluated by analog engine or digital engine. Question regarding designing a universal analog assertion language (like PSL with flavors for Verilog-AMS, VHDL-AMS, System-C) was discussed. It was felt that this working group should focus its efforts on extending SVA instead of trying to define a universal language. Questions were raised (by Ken Bakalar?) about the potential problems/issues for extending SVA to dense time domain and whether we could leverage some of the work done for extending PSL. Dejan mentioned that fundamentally there does not seem to be a big hole to extend SVA (regular expressions) that includes dense time. The challenge might be in the integration of the LTL temporal operators + dense time with regular expressions. There has been some work in this area which can be looked into. (Refer: http://www-verimag.imag.fr/~maler/Papers/timed.pdf <http://www-verimag.imag.fr/~maler/Papers/timed.pdf> , http://www-verimag.imag.fr/PEOPLE/Oded.Maler/Papers/kleene.pdf <http://www-verimag.imag.fr/PEOPLE/Oded.Maler/Papers/kleene.pdf> ). John Havlicek mentioned that LTL operators have been added to the P1800 and that all the basic operators were there. He felt that the local variables will probably play an important part in the analog extension to SVA. Dejan mentioned that local variables should be allowed to be used at any time. John said that they should be restricted when they can be assigned but they could be referenced after they were assigned at any point. The work done at IIT Kharagpur was also discussed briefly. The working group did not reach a consensus on whether monitors should be in analog domain and produce digital signals to be used within the digital assertions. Scott Little felt that assertions should not be split. Himyanshu Anand wanted the language to be implementation agnostic and leave it to the simulators to decide to split the work for evaluating the assertions. The question whether analog assertions should control the accuracy of the simulator was discussed. It was felt by a majority and a consensus was reached that accuracy needs to be defined in assertions to have a local affect on the simulation rather than a global affect. The basic things to extend SVA to analog properties would be to add real (continuous) domain signals to SVA and allow inequalities to be defined inside assertions involving reals along with the notion of asynchronous time and handling intervals. The work will involve combining temporal logic with regular expressions and defining them over dense time (or asynchronous time) It was decided that Kevin's proposal did not belong to this working committee. Frequency analysis properties along with parametric sweeps were also discussed. Prabal asked whether PSL was looked at and why SVA was chosen for the analog property extension work. Himyanshu mentioned that SVA was chosen because there was a parallel work going to start soon that will integrate System Verilog into Verilog-AMS, thus extending SVA would facilitate that integration. Ken Bakalar mentioned that extending SVA with small things (reals and inequalities involving reals) would allow rapid prototyping of analog properties that would require changes to only to digital engine. David Sharrit had raised the question whether the analog property language will replace the MDL and proprietary .measure statements. Himyanshu felt that it would be complimentary rather than a super set of such features. Scott mentioned that there are features in .measure like languages which do not sit well the notion of assertion or property. Himyanshu mentioned that there might be some features which will require to be added to the assertion language but probably not all, like the frequency calculation. Scott added some other features which probably should be accessible from the assertion language like slew rate, settling time, etc. Name Company 18-Jun-08 18-Aug-08 23-Sep-08 7-Oct-08 21-Oct-08 Erik Seligman Intel 1 1 1 1 1 Thanapoom Lertpanyavit Intel 1 1 1 1 1 David Smith Synopsys Mike Demler Synopsys 1 1 1 1 1 Ed Cerny Synopsys 1 1 1 1 Venkataramanan Srinivasan Synopsys 1 1 Dave Cronauer Synopsys 1 1 1 1 1 Prabal Bhattacharya Cadence 1 1 Scott Cranston Cadence 1 Adam Sherer Cadence 1 Walter Hartong Cadence Kishore Karnane Cadence 1 Don O'Riordan Cadence Ned Utzig Cadence Martin O'Leary Cadence 1 1 Dennis Brophy Mentor Graphics 1 1 Kenneth Bakalar Mentor Graphics 1 1 1 1 Kevin Jones Individual Contributor 1 1 1 1 Patrick O'Halloran Tiburon Design Automation 1 1 1 David Sharrit Tiburon Design Automation 1 Marek Mierzwinski Tiburon Design Automation 1 1 1 Dejan Nickovic Verimag 1 1 1 Pallab Dasgupta IIT-KGP Sri Chandra Freescale 1 1 1 1 Dave Miller Freescale 1 1 John Havlicek Freescale 1 1 1 1 1 Hillel Miller Freescale 1 1 1 1 Scott Little Freescale 1 1 1 1 Himyanshu Anand Freescale 1 1 1 1 1 Brian Mulvaney Freescale 1 1 Phillip LaPlace Freescale 1 Daniel Christopher Freescale 1 Linda Lin Freescale 1 Saurabh Garg Freescale 1 1 1 Benjamin Ehlers Freescale 1 1 Zhang Yonggang Freescale Bill Read Freescale 1 Fais Yaniv Freescale 1 Mark Kole NXP Jasmine NSC 1 David Tamura NSC Kevin Cameron True Circuits 1 1 1 David Jonathan Qualcomm 1 Laisne Michael Qualcomm 1 Li Xiang Qualcomm 1 Attendance 19 18 21 21 17 Himyanshu Anand EDA Strategy, Vendor Relation and Customer Collaboration, Design Technology Organization, Freescale Semiconductor 7700 W. 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