Minutes of Verilog-AMS committee meeting - 13th Nov 2008

Attendees:
* Marq Kole, NXP
* Chris Vigil, IEEE
* Martin O'Leary, Cadence
* Dave Cronauer, Synopsys
* Dave Miller, Freescale
* Marek Mierzwinski, Tiburon
* Sri Chandra, FSL

Minutes:

* New call times:
   - 6.30a seems to be acceptable to most (except for Australia). We 
will follow this for a while and depending on request for active 
participation from Australia this might have to be revisited/modified.

* Discussion on entity vs individual standard and feedback from member 
companies (representatives)
   - Chris informed that the charges for entity standard for member 
participation has increased marginally from $3900 to $4000. Its unclear 
whether there has been any change in fee for the individual standards 
voting rights. Chris to clarify
   - It was mentioned that the committee can decide to change the option 
from individual to entity (or vice-versa) at a later date. However a PAR 
needs to be raised again and approved by IEEE board and any fees paid 
will not be refunded.
   - The payment is on yearly basis from the date of payment. Entities 
can chose not to pay and have voting rights for particular year. Working 
group will have additional clauses on voting based on attendance etc.
   - Martin wanted clarification whether technical editing will be part 
of the service provided for the fees under entity standard. Chris 
clarified that it is not the case and that has to be separately born by 
the members of the working group.
   - The decision on whether entity or individual standard needs to be 
done at the time of submission of PAR approval
   - The interest seems to be more towards individual standards from NXP 
and Tiburon given the cost effectiveness of that option. Freescale 
prefers the corporate standard for the work, however may not apply for 
the voting rights. Cadence and Synopsys are expected to get back with 
their response. It will be good to get feedback from other regular 
participants in the committee also, who were unable to attend the call.
   - There needs to be atleast 3 voting members in the entity standard.
   - It is still unclear whether intermediate release of AMS 
enhancements and assertions work be done under Accellera even if the 
SV-AMS committee is executed as part of P1800 working group as a dot 
standard. This query has been sent to Michael Kipness who has been 
assigned project manager for AMS from IEEE.

* PAR approval status:
   - DASC approved formation of a working group 3 weeks ago.
   - Its unclear how many official positions needs to be there as part 
of the working group. Its also unclear on exact deliverables that need 
to be submitted for PAR approval. Verilog-AMS LRM already has an 
approved LRM2.3 version under Accellera. Also, unclear about 
intermediate releases within Accellera. These queries has been sent to 
Michael Kipness from IEEE.
   - There is a presentation to the IEEE DASC board next week on the 
status of the working group and PAR (Nov 20th, 11am pacific)

Next call: Nov 20th, 6.30a pacific

Regards,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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