Cancelled: Meeting on Dec 30th, 2008 is cancelled due to holiday season. Next Meeting on January 13th, 2009 Attendance: At the end, please correct if I missed someone. Meeting Minutes from John Havlicek Meeting 2008-12-16 ------------------ - Committee to go forward, introduce requirements for analog assertions AMS. - KB: Putting extension in Verilog AMS doesn't solve problem for customer who has mixed signal design. Analog portions need to be integrated with digital (20% analog with 80% of problems, 80% digital with 20% of problems). Pure analog designer operating only in AMS -- maybe they do not exist. Big market is digital dominated mixed signal design. Attach some analog to this in some verification runs. This is an argument against putting the extension in Verilog AMS. - ??? can you clarify interface? KB: AMS has wreal wire. SV has real port type or variable, but it is not net-like. Connectivity information is not kept. The AMS resolution algorithms need this connectivity information. - HA: If we extend SVA and make it a part of AMS extended language, how would this prevent prototyping? KB: What has to come along with SVA? Clocking blocks? - JH: Outlined what is typically in assertion module. Assertions, modeling code, supporting tasks and functions, covergroups and coverage code. - What of AMS needs to be imported into SV in order to define the extensions in SV? KB: There is an interface issue. - KB: Heart of matter is dense time, purely digital issue. Make assertions on dense rather than clocked time. Prerequisite to any consideration of analog crossings. As a practical matter it has to be implemented by SV teams. - Prabal: There is a part of AMS extension needed. Some SVA extension needed to get meaningful things done. This is not something we can do without some SVA-AMS effort. Think incrementally about what features need to be brought into SV. - DM: Verilog AMS committee hasn't started up really, and won't until next year. - 1800 to support dense time. Real expressions in booleans. - DN: SVA to dense time is a semantic issue. - KB: Can we superimpose dense time semantics on top of clock semantics and have a single language for both? DN: Map digital to dense time. Other direction can lose information. KB: A dense time language for SV is different from the clock event semantics. - Prabal: Can users try to mix and match digital sensitivities with analog sensitivities? KB: Mix dense time and clocked time. Prabal: @(cross ...) is not really boolean. KB: cross has an event-like nature. Prabal: Syntax issue. Can I import mixed signal events into it? - JH: I am hopeful that the current digital assertion semantics could be overlayed on top of continuous time without any severe impact to the digital assertion usage model. This would open the way to import event controls from analog side. - JH: Users are approximating analog assertions with digital. They are using auxiliary variables to get the effect of comparison expressions involving reals. They are using high frequency clocks to get sufficient sampling to be confident. They are making engineering decisions about the tradeoffs involved. Meeting Minutes from Himyanshu Anand ----------------------------------------------------- The question of the committee's work going to System Verilog (P1800) or Verilog-AMS was raised. P1800 is winding down it's work related to 2009 release. As such, it is unlikely it will open a new PAR anytime soon (2-3 years). On the other hand VAMS is starting up new work and may be able to incorporate analog assertions work. There did not seem to be a consensus on the where the analog assertions should reside. Dave Miller was of the opinion that some initial work needs to be done in System Verilog, that way SV-VAMS integration will inherit the basic support in VAMS for analog assertions. Ken believes that the SVA should be extended to dense time semantics. Himyanshu mentioned that the extension could be part of the VAMS language and left for implementation to decide on how to do the actual partition. Also, that later on when the P1800 opens up, some parts of the extension could be pushed back into System Verilog as appropriate. John mentioned that we should continue on extension work and decide later on the committee. The following needs to be addressed - dense time semantics of assertions in SVA, real relational support and special functions defined for the analog properties like (frequency calculator, mean etc.). Dejan mentioned that moving dense time to digital time could possibly be done, but will incur loss of information. Prabal mentioned that @cross is not boolean. Can it be viewed as a boolean event by the digital domain in a mixed signal simulator. Prabal also wanted to know about the interface resolution that Ken talked about. Dave Miller wanted to know whether SVA supported PLI calls. John mentioned that assertions (SVA) could call functions and tasks but was not sure whether that allowed PLI calls. Ken asked who were the end users and what kind of assertions they liked to write. John, Scott and Himyanshu mentioned that the users were already using a mixture of System Verilog/VAMS using workarounds since there was no direct tool support for analog assertions. The examples that Freescale shared with the committee were motivated by what the users are/trying to do with assertions in their designs. There was a discussion on unifying time semantics, using @cross naturally across the assertions and how @cross determines the time step and its comparison with a digital overhead of a high frequency clock running in the background. Ken mentioned that designs are 80% digital with 20% problems and 20% analog with 80% problems. As an example of the interface issue Ken metioned the lack of wreal in digital (SV), and the fact that real variable is not really equivalent to wreal wire in VAMS. Such interface issues would need to be sorted out. Ken wants SV teams to implement the analog extensions. Scott and Himyanshu raised the issue that some constructs are purely analog, like @cross, voltage and current probes. Thus, as it is, the question is not purely digital nor is it purely analog but a mixture of both. Hence, needs to be in both SVA and VAMS. Prabal from Cadence believes that it will have to be addressed by both. The conclusion: Continue with the work to define the extensions and the work required for analog assertions. Revisit the question of which committee this needs to go into later. Attendees: Total 12 ------------------------ Erik Seligman Intel Mike Demler Individual Contributor Prabal Bhattacharya Cadence Kishore Karnane Cadence Kenneth Bakalar Mentor Graphics Patrick O'Halloran Tiburon Design Automation David Sharrit Tiburon Design Automation Dejan Nickovic EPF Lausanne Dave Miller Freescale John Havlicek Freescale Scott Little Freescale Himyanshu Anand Freescale -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Dec 16 11:55:01 2008
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