Updated: Analog System Verilog Assertions

From: Anand Himyanshu <HIMYANSHU.ANAND_at_.....>
Date: Fri Jan 30 2009 - 13:31:08 PST
When: Occurs the fourth Tuesday of every 1 month effective 2/24/2009 from 10:00 AM to 11:30 AM (GMT-06:00) Central Time (US & Canada).
Where: Time: 10:00 AM - 11:30 AM Central Standard Time (Austin Time) (GMT - 6:00)

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Time: 10:00 AM - 11:30 AM Central Standard Time (Austin Time) (GMT - 6:00)

Changing to monthly meeting.

- Twiki for Analog Assertions committee work: http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/AmsAssertions
- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Some documents released to the committee can be found at  http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/

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Received on Fri Jan 30 13:31:56 2009

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