RE: Expressions as part of port connections in module instantiations

Support of "assign win = V(a);" would require a D2A event to be created
to execute this continuous
assign every time there is a change in V(a), however small.

This would generally lead to serious performance issues.

Hence it is best to disallow this if it is not allowed already.

thanks,
--Martin

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Scott Cranston
Sent: Tuesday, May 05, 2009 1:31 PM
To: David Miller; Verilog-AMS LRM Committee
Subject: RE: Expressions as part of port connections in module
instantiations

It follows the same semantics as continuous assignments, i.e. if you
*can* do:

assign win = V(a);

then you *can* do this.

If you *can't* do:

assign win = V(a);

then you *can't* do this.

Regards, Scott


-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of David Miller
Sent: Tuesday, May 05, 2009 16:25
To: Verilog-AMS LRM Committee
Subject: Expressions as part of port connections in module
instantiations

Hello all,
I have a question regarding the use of expressions as a port connection
when instantiating a module.

module parent(a);
   electrical a;
   child ch1(V(a));
endmodule

module child(win);
   input win;
   wreal win;
   ....
endmodule

Notice here I am passing V(a) (as an expression) into child. Based on
the grammar this is allowed also in section 6.2 Module Instantiation we
have the
comment:

"An expression can be used for supplying a value to a module input port
if it is a digital port."

Was it intended to allow continuous analog values to be passed like this
into digital or is this an oversight. I always thought the use of
expressions in the port connection was to handle passing of literal
values:

   child ch1(1'b1);

that sort of thing.

Cheers...
Dave


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