Re: Expressions as part of port connections in module instantiations

[Previous reply didn't make it to the reflector]

My question is what's the semantic difference between

    child ch1(a)

and

    child ch1(V(a))

- and I would say that the latter is a signal-flow connection of the
voltage of node 'a' (a PWL real value), as such it does not require an
A2D. Any digital process sensitive to the port in ch1 (assign/@) gets an
event at acceptance if V(a) changes.

Seems like a reasonable thing to want to do in a mixed-signal test-bench.

Kev.

David Miller wrote:
> Hello all,
> I have a question regarding the use of expressions as a port
> connection when instantiating a module.
>
> module parent(a);
>   electrical a;
>   child ch1(V(a));
> endmodule
>
> module child(win);
>   input win;
>   wreal win;
>   ....
> endmodule
>
> Notice here I am passing V(a) (as an expression) into child. Based on
> the grammar this is allowed also in section 6.2 Module Instantiation
> we have the comment:
>
> "An expression can be used for supplying a value to a module input
> port if it is a digital port."
>
> Was it intended to allow continuous analog values to be passed like
> this into digital or is this an oversight. I always thought the use of
> expressions in the port connection was to handle passing of literal
> values:
>
>   child ch1(1'b1);
>
> that sort of thing.
>
> Cheers...
> Dave
>
>


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