RE: Expressions as part of port connections in module instantiations

Hi Jonathan:

A driving motivation for this capability is to be able to create AMS
assertions (in a suitable extension of SVA) within an appropriate
container (e.g., a module or a SystemVerilog checker) and hook the
assertions up to the various AMS data that they need to observe.  The
instance could be an instance of that container.

J.H.

(not sure if this will go to the verilog-ams reflector ...) 

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Jonathan David
Sent: Friday, May 08, 2009 2:02 AM
To: Kevin Cameron; Miller Dave-A17239
Cc: Verilog-AMS LRM Committee
Subject: Re: Expressions as part of port connections in module
instantiations


Wow.. 
so not instead of the ports connecting to Nets (like pin connect to
wires) you are now connecting the pin to the color(voltage) of the wire?


of course I might want to do that for simulation.. but I might also want
to connect to a different representation of the subblock that should
connect to the whole wire? 
After all this isnt VHDL.. do we want the instantiation to vary
depending on the represenation underneath? 


 Jonathan David
j.david@ieee.org
jb_david@yahoo.com
http://ieee-jbdavid.blogspot.com
Mobile 408 390 2425



----- Original Message ----
From: Kevin Cameron <edaorg@v-ms.com>
To: David Miller <David.L.Miller@freescale.com>
Cc: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Sent: Thursday, May 7, 2009 6:36:34 PM
Subject: Re: Expressions as part of port connections in module
instantiations

[Previous reply didn't make it to the reflector]

My question is what's the semantic difference between

    child ch1(a)

and

    child ch1(V(a))

- and I would say that the latter is a signal-flow connection of the
voltage of node 'a' (a PWL real value), as such it does not require an
A2D. Any digital process sensitive to the port in ch1 (assign/@) gets an
event at acceptance if V(a) changes.

Seems like a reasonable thing to want to do in a mixed-signal
test-bench.

Kev.

David Miller wrote:
> Hello all,
> I have a question regarding the use of expressions as a port 
> connection when instantiating a module.
>
> module parent(a);
>   electrical a;
>   child ch1(V(a));
> endmodule
>
> module child(win);
>   input win;
>   wreal win;
>   ....
> endmodule
>
> Notice here I am passing V(a) (as an expression) into child. Based on 
> the grammar this is allowed also in section 6.2 Module Instantiation 
> we have the comment:
>
> "An expression can be used for supplying a value to a module input 
> port if it is a digital port."
>
> Was it intended to allow continuous analog values to be passed like 
> this into digital or is this an oversight. I always thought the use of

> expressions in the port connection was to handle passing of literal
> values:
>
>   child ch1(1'b1);
>
> that sort of thing.
>
> Cheers...
> Dave
>
>


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