Verilog-AMS committee meeting - 14 May 2009

Hi all,

I am hoping that LRM 2.3.1 would be approved by the board and published 
very soon. I thought I will call for a meeting to discuss, understand 
and plan the next key steps.

[It will be good for assertions sub-committee members also to attend 
this call]

- I would like to discuss the Verilog-AMS merge with IEEE and the impact 
of assertions language development. I have been discussing with 
Accellera on how this would affect the development & release of 
Verilog-AMS and would like to discuss my thoughts (on various options) 
and hear feedback from the community on this.

- Key priorities for Verilog-AMS work (recent postings on connect 
modules, enhancements required to support ASVA, start on SV-AMS integration)

Date: 13 May 2009

Call-In Details:
USA Toll Free: 877-346-8823
USA Toll: +1-203-320-0407
Passcode: 602538

Time:
06:30am US Pacific
08:30am US Central
09:30am US Eastern
15:30pm Eindhoven
19:00pm Noida
23:00pm Adelaide

Regards,
Sri


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.