[Fwd: Minute of Verilog-AMS committee meeting : 14 May 2009]

Hi all,

I just realized that there was an email from Geoffrey mentioned that 
there was an issue with the email being sent out. I am not sure whether 
the minutes that I sent out last week actually reached you. I think 
there was an issue with the "To" list being too long since i had issue 
with the AMS reflector. Hopefully this one reaches you all.

Regards,
Sri

-------- Original Message --------
Subject: Minute of Verilog-AMS committee meeting : 14 May 2009
Date: Fri, 15 May 2009 09:45:39 +0530
From: Sri Chandra <sri.chandra@freescale.com>
Organization: Freescale Semiconductor Inc.
To: ...
CC: Verilog-AMS LRM Committee <verilog-ams@eda.org>

Hi all,

Please find the notes from yesterday's meeting. If i have missed
somebody in the list my apologies. Also, I couldnt keep pace with the
discussions, so I have listed the key points based on memory. If you
feel I have missed something (or misrepresented any detail) please feel
free to reply to this email. Thanks once again for the good discussions,
we may not be closer a decision but I believe we are heading in the
right directions in terms of understanding what is required and what the
community needs are from this standards effort to make the right choice.

Regards,
Sri

Date: 14 May 2009

Attendees:
Himyanshu Anand, Freescale
Ken Bakalar, Mentor
Prabal Bhattacharya, Cadence
Sri Chandra, Freescale
Geoffrey Coram, Analog Devices
Dave Cronauer, Synopsys
Graham Helwig, ASTC
Jim Lear, Zarlink
Top Lertpanyavit, Intel
Scott Little, Freescale
Dave Miller, Freescale
Patrick O'Halloran, Tiburon
Martin O'Leary, Cadence


Notes from the meeting:

Discussion was primarily based on seeking further feedback on whether to
move to IEEE or stay with Accellera for the Verilog-AMS & the assertions
committee.

    * There was discussion last year to move Verilog-AMS from the
      Accellera standards to IEEE, and following that a presentation was
      made to DASC committee. The committee approved working on a PAR
      for Verilog-AMS, which on approval will create a study group in
      IEEE to work on SystemVerilog integration with AMS (SV-AMS) as
      part of the P1800 dot standard. The focus of the study group as
      per the presentation made to DASC board was to focus on SV-AMS
      integration.
    * The assertions subcommittee has been working on language
      extensions to SVA for analog. These language extensions require
      changes in Verilog-AMS language as well as SV-2009 to be able to
      support the ASVA features.
    * The concern being discussed mainly was whether moving to IEEE for
      SV-AMS integration delay the release of ASVA. The goal of IEEE
      study group as per the original approval to work on a PAR is to
      focus on SV-AMS integration and release it as part of a P1800 dot
      standard. This release is currently expected no early than 2013,
      and going by the efforts required for P1364 integration, this is a
      good estimate (if not optimistic). It is very likely that the ASVA
      extensions will be available much earlier.
    * The release of ASVA would require an updated version (standards
      release) of the Verilog-AMS language as well as an updated version
      of SystemVerilog (irrespective of where the work is done). Is this
      possible within the charter of IEEE for Verilog-AMS IEEE P1800 dot
      standard. Need to ensure that the main SV BC committee are
      agreeable to the amendments to SystemVerilog standards required
      for ASVA.
    * The assertions sub-committee will work on ASVA extensions and also
      the changes required in SV committee and the main Verilog-AMS
      committee will work on the VAMS extensions (on top of the other
      mixed signal related enhancements and SV-AMS).

There was discussion on why is there a need to move to IEEE from
Accellera, and subsequent benefits

    * Typically Accellera expects the standards that they are involved
      in, once stable, are migrated to IEEE and the worked carried on
      within the IEEE standards. The work in Accellera is to ensure the
      language reaches a good degree of consensus within its charter and
      has a stable language before the donation of the standard to IEEE.
    * Comments were made on the fact that having an IEEE standards,
      involves a broader audience, preference for IEEE standards from
      customer point of view (for EDA vendors) and also wider scrutiny
      of the language standards which is very important. The processes
      within IEEE forum ensures more stringent measures to add features
      and the release of standards
    * The approval & release of new versions of a standard might take
      much longer within IEEE. However this is not necessarily viewed as
      a bad side effect. There might be lot of accidental discussions on
      top of the essential discussions that need to be addressed due to
      a broader reach of the IEEE standards and hence might delay the
      process within IEEE.
    * The voting rights within IEEE are however expensive (used to be
      USD 4000+ per project per year), but this is being revised. The
      plan for the P1800 dot standard is currently to approach it as a
      corporate standard.


Questions that were raised and need to be answered. [I will follow this
up with Accellera and hopefully get responses before the next meeting]

    * Is it possible to change the charter for the work done under IEEE
      to state that a Verilog-AMS enhanced version along with SV
      enhancements will be released earlier to the SV-AMS integration
      work? If this is possible, then we can identify this as the first
      goals and include any enhancements targeted towards ASVA and other
      mixed signal enhancements in the pipeline for VAMS.
    * There were queries on P1800 dot standard releases and whether the
      dot standards need to be aligned with the main P1800 release. The
      consensus from people in the committee aware of the IEEE workings
      was, this is not the case. The dot standards can come up with
      their own timeframes for release. The VHDL-AMS dot standard is out
      of sync with VHDL release time frames.
    * Funding for release of a standard? Who will fund this release.
      Need to get back to IEEE on this.


Next meeting: Hopefully, we will have clarification on the above queries
and proceed further. I plan to call the next meeting on 21st of May
assuming I have further information on the questions above.

Regards,
Sri





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