RE: [Fwd: Re: [Fwd: Re: Verilog AMS update]]

Hi Sri,

When will a (cleaned-up?) version of the LRM 2.3.1 become available on the Verilog-AMS standardization website?

Cheers,
Marq


Marq Kole
Product Manager AMSRF Simulation
NXP Semiconductors / Corporate I&T / Design Technology & Flows
________________________________________
From: owner-verilog-ams@server.eda.org [owner-verilog-ams@server.eda.org] On Behalf Of Sri Chandra [sri.chandra@freescale.com]
Sent: Tuesday, June 02, 2009 06:07
To: Verilog-AMS LRM Committee
Subject: [Fwd: Re: [Fwd: Re: Verilog AMS update]]

All,

Congratulations! The LRM 2.3.1 has been approved by the Accellera Board.
Thanks to all for the hard work that went into this revision. We were
able to fix a whole bunch of minor errors and provide a better standards
for the community to use. Also, thanks to Dave Miller for helping out
with the technical edits to the documentation to be able to release it
in such a quick time frame.

Regards,
Sri

-------- Original Message --------
Subject:        Re: [Fwd: Re: Verilog AMS update]
Date:   Mon, 1 Jun 2009 10:07:28 -0700 (PDT)
From:   Karen Pieper <karen_l_pieper@yahoo.com>
To:     Sri Chandra <sri.chandra@freescale.com>, vhberman@ieee.org
References:     <4A23977A.5070103@freescale.com>



Hi, Sri,

The Accellera Board approved the revised standard today.  Congratulations!

K





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