Date: 16th July 2009 Attendees: Dave Miller, Freescale Sri Chandra, Freescale Ian Wilson, Berkeley DA Martin O'Leary, Cadence Marq Kole, NXP Dave Cronauer, Synopsys Ken Bakalar, Mentor Meeting was spent going through the more of the open Mantis items and categorizing them into the four separate buckets: - cleanup (minor issue) - AMS enhancements (extension to Verilog-AMS language) - ASVA extension (requirement to support ASVA work) - SV-AMS integration Based on the attached email below, we have covered/categorized items: 830, 2806, 2805, 2803, 2792, 2594, 2590, 2567, 2459, 937, 940, 821, 2566, 2281, 1471, 874, 2378, 2162, 866, 2343, 1754, 1854, 2161, 2160, 2159, 828, 1765, 1638, 848, 831, 820. The following issues require further investigation / information from the owner, before they can be correctly categorized. 2160 - reals and integers should be able to drive event-driven ports: We were a little unsure exactly what was required from this ticket. May need to follow up with Ken for further clarification. 828 - Handling of light weight conversions: (a2d, d2a) used through behaviour: It is not clear under what circumstances we would insert these light weight connect modules. Need to follow up with Kevin. An example would also be great to understand the context of these conversions. 831 - Ambiguity in indexing of named vector branches as specified in LRM: Follow up request was to check with SV to see if they have any similar situations with respect to indexing. If so we can use that, else we can default the indexing from 0 to length on branches, regardless of the indexing used on the nodes. 820 - Discipline Compatibility issues. This item requires further clarification. We are unsure if it is trying to address the issue of which abstol do we use when connecting electrical to my_electrical? Also when we check for discipline compatibility to we take into account user defined attributes on the discipline? Also in what context does the resolveTo statements apply, is it only when determining which connect modules to insert or is it also used when determining if electrical and my_electrical can be connected together. Next Meeting: 23rd July 2009 Agenda : Go through the remaining issues: 829, 825, 935, 904, 936, 934, 955, 839, 840, 845, 876, 814, 813. Call-In Details: USA Toll Free: 877-346-8823 USA Toll: +1-203-320-0407 Passcode: 602538 Time: 06:30am US Pacific 08:30am US Central 09:30am US Eastern 15:30pm Eindhoven 19:00pm Noida 11:00pm Adelaide Cheers... Dave -- ============================================== -- It's a beautiful day -- Don't let it get away -- -- David Miller -- Design Technology (Austin) -- Freescale Semiconductor -- Ph : 512 996-7377 Fax: x7755 ============================================== -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
attached mail follows:
Hi all, I have gone through the open items and placed them into one of the four categories: - cleanup (minor issue) - AMS enhancements (extension to Verilog-AMS language) - ASVA extension (requirement to support ASVA work) - SV-AMS integration We can discuss tomorrow whether the categories I have distributed the items into are correct or not. Cheers... Dave Id: 830 (http://www.verilog.org/mantis/view.php?id=830) Summary: Support for breaking out of loops Category: SV-AMS integration Id: 2806 (http://www.verilog.org/mantis/view.php?id=2806) Summary: Direction argument in last_crossing not optional in 4.5.10 Category: Cleanup Id: 2805 (http://www.verilog.org/mantis/view.php?id=2805) Summary: Interpolation vs synchronisation of analog values in digital Category: ASVA extension Id: 2803 (http://www.verilog.org/mantis/view.php?id=2803) Summary: Why is access to hierarchical port branch syntax disallowed (I(<a1.p>)) Category: Cleanup / AMS enhancements Id: 2792 (http://www.verilog.org/mantis/view.php?id=2792) Summary: $monitor support in Table 9-1 wrong Category: Cleanup Id: 2594 (http://www.verilog.org/mantis/view.php?id=2594) Summary: Ambiguity in list_of_ports syntax item definition. Category: SV-AMS integration Id: 2590 (http://www.verilog.org/mantis/view.php?id=2590) Summary: Semantics of _function_call rules Category: SV-AMS integration Id: 2567 (http://www.verilog.org/mantis/view.php?id=2567) Summary: Syntax/rules for handling escaped quotes Category: Cleanup Id: 2459 (http://www.verilog.org/mantis/view.php?id=2459) Summary: Wrong hyphenation on page 214 Category: Move to Resolved Id: 937 (http://www.verilog.org/mantis/view.php?id=937) Summary: allow discipline attribute change/addition on per net basis Category: AMS enhancements Id: 940 (http://www.verilog.org/mantis/view.php?id=940) Summary: additional math operator support Category: SV-AMS integration Id: 821 (http://www.verilog.org/mantis/view.php?id=821) Summary: Allowing C-style include syntax for files Category: SV-AMS integration Id: 2566 (http://www.verilog.org/mantis/view.php?id=2566) Summary: VPI related issues in LRM v2.3 Category: AMS enhancements (but may become redundant with SV-AMS integration). Id: 2281 (http://www.verilog.org/mantis/view.php?id=2281) Summary: disciplines and wreal Category: AMS enhancements Id: 1471 (http://www.verilog.org/mantis/view.php?id=1471) Summary: cross/above expr_tol default value is not defined in LRM Category: Move to resolved Id: 874 (http://www.verilog.org/mantis/view.php?id=874) Summary: (Ann E) clarifications on usage of vsource Category: Cleanup (references to vsource should be removed). Id: 2378 (http://www.verilog.org/mantis/view.php?id=2378) Summary: Deprecate wreal Category: AMS enhancements Id: 2162 (http://www.verilog.org/mantis/view.php?id=2162) Summary: Need ability to assign z to wreal Category: AMS enhancements Id: 866 (http://www.verilog.org/mantis/view.php?id=866) Summary: Back-Annotation support is non-existant Category: AMS enhancements / SV-AMS integration Id: 2343 (http://www.verilog.org/mantis/view.php?id=2343) Summary: Connect module instances should be on lower side of ports Category: AMS enhancements Id: 1754 (http://www.verilog.org/mantis/view.php?id=1754) Summary: Support for auto-connecting implicit ports (e.g. power supplies) Category: AMS enhancements Id: 1854 (http://www.verilog.org/mantis/view.php?id=1854) Summary: parameter aliases for hierarchical system parameters Category: AMS enhancements Id: 2161 (http://www.verilog.org/mantis/view.php?id=2161) Summary: register access from analog block Category: SV-AMS integration Id: 2160 (http://www.verilog.org/mantis/view.php?id=2160) Summary: reals and integers should be able to drive event-driven ports Category: AMS enhancements Id: 2159 (http://www.verilog.org/mantis/view.php?id=2159) Summary: Contributing to a port branch Category: AMS enhancements Id: 828 (http://www.verilog.org/mantis/view.php?id=828) Summary: Handling of light weight conversions: (a2d, d2a) used through behaviour Category: AMS enhancements Id: 1765 (http://www.verilog.org/mantis/view.php?id=1765) Summary: Correction of names/insertion point for connect modules Category: AMS enhancements Id: 1638 (http://www.verilog.org/mantis/view.php?id=1638) Summary: (Ann D) physical constants change Category: Cleanup (just make sure we adhere to NIST) Id: 848 (http://www.verilog.org/mantis/view.php?id=848) Summary: (Sec 4, Ann A) ddx is currently restricted as analog operator Category: Cleanup (I think this is addressed and can be closed) Id: 831 (http://www.verilog.org/mantis/view.php?id=831) Summary: (Sec 3?) Ambiguity in indexing of named vector branches as specified in LRM Category: Cleanup (no range given, indexing should be from 0 to length) Id: 820 (http://www.verilog.org/mantis/view.php?id=820) Summary: (Sec 8) Discipline Compatibility issues Category: AMS enhancements Id: 829 (http://www.verilog.org/mantis/view.php?id=829) Summary: (Sec 12) Issues with VPI Category: AMS enhancements / SV-AMS integration Id: 825 (http://www.verilog.org/mantis/view.php?id=825) Summary: (Sec 8) Resolving variables to the domain based on assignment context is ambigous. Category: AMS enhancements Id: 935 (http://www.verilog.org/mantis/view.php?id=935) Summary: V(vin[i]) for modeling multiplexers Category: AMS enhancements Id: 904 (http://www.verilog.org/mantis/view.php?id=904) Summary: No support for absolute delay in the digital context Category: SV-AMS integration Id: 936 (http://www.verilog.org/mantis/view.php?id=936) Summary: enhanced analog/digital event control Category: AMS enhancements Id: 934 (http://www.verilog.org/mantis/view.php?id=934) Summary: remove restrictions on analog operators Category: AMS enhancements Id: 955 (http://www.verilog.org/mantis/view.php?id=955) Summary: conditional net discipline coercion Category: AMS enhancements (I think this is already addressed). Id: 839 (http://www.verilog.org/mantis/view.php?id=839) Summary: Default values of idt & ddt nature for derived natures should be clarified in LRM Category: Cleanup Id: 840 (http://www.verilog.org/mantis/view.php?id=840) Summary: Support for system task $isPortsShorted Category: AMS enhancements Id: 845 (http://www.verilog.org/mantis/view.php?id=845) Summary: Restrict usage of type of analog variable that can be used in 'assign' statements Category: AMS enhancements (sort of related to Item: 2805) Id: 876 (http://www.verilog.org/mantis/view.php?id=876) Summary: Vector range when they differ in inout and discipline declaration Category: Cleanup (seems a simple sentence in LRM would suffice) Id: 814 (http://www.verilog.org/mantis/view.php?id=814) Summary: Support for global variables using dynamic parameter Category: AMS enhancements / SV-AMS integration. Id: 813 (http://www.verilog.org/mantis/view.php?id=813 ) Summary: Support direct import of spice primitives (as defined in Annex E) into Verilog-AMS Category: SV-AMS integration (I think this issue could be closed, not required??) -- ============================================== -- It's a beautiful day -- Don't let it get away -- -- David Miller -- Design Technology (Austin) -- Freescale Semiconductor -- Ph : 512 996-7377 Fax: x7755 ==============================================Received on Wed Jul 22 09:46:13 2009
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