RE: UDP net with discipline identifier

If you are using the ams discipline to know whether this is a 1.3 or 2.2 v logic, or even CML type output, I think you might want to allow a discipline to be declared for a UDP. 
Other wise you would not be able to have a std cell that is just a udp. You'd have to wrap the udp at a level where you can declare a discipline.

-----Original Message-----
From: David Miller <David.L.Miller@freescale.com>
Sent: Tuesday, August 11, 2009 6:25 AM
To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Subject: Re: UDP net with discipline identifier

Well the only discipline_identifier that would make sense would be the discrete 
- dlogic or wire.

I don't know enough about digital, but if it doesn't make sense to have a UDP 
output declared as dlogic or wire then I guess it should be removed.

However, the inclusion of the discipline_identifier is the only deviation we 
made from 1364.
Perhaps Graham may have more info on why we made this addition?

Regards
Dave


Surya Pratik Saha wrote:
> Hi,
> I have seen following rule in Verilog AMS 2.3.1:
> *udp_output_declaration ::=
> { attribute_instance } output port_identifier
> | { attribute_instance } output [ discipline_identifier ] reg 
> port_identifier [ = constant_expression ]
> udp_input_declaration ::= { attribute_instance } input 
> list_of_port_identifiers
> udp_reg_declaration ::= { attribute_instance } reg [ 
> discipline_identifier ] variable_identifier
> *
> But I think there is no meaning to add discipline identifier with udp 
> nets. So LRM needs a correction here. Please let me know if I am wrong 
> here, otherwise I will file a Mantis.
> 
> -- 
> Regards
> Surya
> 
> 
> -- 
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