Minutes of Verilog-AMS committee meeting - 3 Sept 2009

Date: 3 Sept 2009

Martin O'Leary, Cadence
Dave Cronauer, Synopsys
Dave Miller, Freescale
John Havlicek, Freescale
Graham Helwig, ASTC
Ian Wilson, Berkeley DA
Sri Chandra, Freescale

(If I have missed somebody my apologies).

Minutes of the meeting:

* Plans for ASVA extensions, SV-AMS and Verilog-AMS enhancements
   - The plan for the Verilog-AMS technical committee is to move forward
with doing assertions extensions to SVA (ASVA) under Accellera.
   - The work on assertions will happen in parallel with the SV-AMS
integration activities and the donation of Verilog-AMS standard to IEEE
will be considered after this release. At this time, the expectation is
for some of the key SV-AMS issue in terms of integration to be resolved
prior to the donation to IEEE
   - The Verilog-AMS enhancements that have been identified to be
included in the language and the minor bug fixes will be planned to be
rolled into the release containing assertions extensions. If there is a
need to release an interim version of these bug-fixes and enhancements
this can be considered. At this point, the plan is for this to be part
of assertions release.
   - Accellera will be notified about the Verilog-AMS technical
committee plans in moving forward with these parallel activities.

* Status of ASVA requirements gathering
   - John gave an update on the status of requirements gathering on
ASVA. The requirements are close to getting finalized pending a voting
on each of the requirements very soon. Currently there are lot of
discussions on supporting access to SV quantities through interface
connections (without impacting Verilog-AMS in a big way. Extensions are
being planned so that this will naturally align with SV-AMS integration
once that is complete.
   - Discussion on whether the vote will be based on individual
requirements or overall document. The preference is to vote on
individual requirements for ASVA.
   - There was also some discussions on voting procedure
(one-company-one-vote etc) and guidelines.
   - The plan is to discuss the voting aspects for ASVA requirements as
part of one of the upcoming committee meetings.

* SV-AMS integration
   - Part of the main Verilog-AMS technical committee will be working on
SV-AMS integration - grammer, semantics etc
   - Ken had earlier raised an aspect on the issue of scheduling
semantics differences between SV and Verilog that might impact the AMS
mixed signal scheduling semantics. Needs to understand this more clearly
and see how it impacts AMS scheduling.
   - Need for Accellera to request IEEE for the P1800-2009 documentation
that will be used as the basis for the AMS integration.

* Volunteers and plans moving forward
   - Need to understand how many volunteers are available for the next
phase of acvities (ASVA extensions, AMS enhancements and SV-AMS
integration). This will help in the planning and prioritizing of the
requirements and also understanding of release timeframes.
   - Dave Miller (Freescale) has started working on some of the minor
fixes which will be reviewed in the upcoming calls, and Graham is
planning to look at some of the initial SV integration issues.

Regards,
Sri


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