RE: @above in analyses other than tran and dc sweep

Just to add yet another point...

I generally stay away from DC sweeps (when I make I-V
curves for IBIS models) because most modern buffers
have lots of flip flops (bi-stable elements) because
of which we usually need a few clock cycles to get
the buffer into a known state.  This would be impossible
in DC sweep mode unless lots of initial conditions would
be set in the netlist, but that is very seldomly done...

Arpad
==========================================================

-----Original Message-----
From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Mark Zwolinski
Sent: Thursday, November 19, 2009 4:50 AM
To: Geoffrey.Coram
Cc: Ian Wilson; verilog-ams@eda.org
Subject: Re: @above in analyses other than tran and dc sweep

...
...
...

One other point. I did a Google search on "spice sweep hysteresis" and 
found this from "SPICE for power electronics and electric power" by M. 
H. Rashid, Hasan M. Rashid, p499 on Google Books: "The most common cause

of failure of the DC sweep analysis is an attempt to analyze a circuit 
with regenerative feedback, such as a Schmitt trigger. The DC sweep is 
not appropriate for calculating the hysteresis of such circuits, because

it is required to jump discontinuously from one solution to another at 
the crossover point." It's slightly off-topic, but they've clearly been 
burned by this. A DC sweep is not the right way to explore hysteresis!

Mark

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.