RE: Minutes of Verilog-AMS committee meeting - 18th Nov 2009

I don't know about that. 
In digital Verilog, wires have capacitance and resolution functions.
And their values are discrete Boolean values (though 4-state). 

Shalom

> -----Original Message-----
> From: owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Kevin Cameron
> Sent: Thursday, November 26, 2009 6:18 AM
> To: Verilog-AMS LRM Committee
> Cc: David Miller
> Subject: Re: Minutes of Verilog-AMS committee meeting - 18th Nov 2009
> 
> David Miller wrote:
> > Date: 18th Nov 2009
> >
> > Objective of this meeting was to go through the "AMS Enhancement"
> > items to identify the ones we want to do / close / group into common
> > items etc.
> > ....
> >
> > Item 2378: Deprecate wreal. Moving to closed. We won't be 
> deprecating
> > wreal.
> >
> 
> The point in deprecating it is that it is an unnecessary construct in
> the language. You can keep the declaration "wreal" if you 
> want, but the
> functionality is really just a degenerate case of a regular 
> wire: with a
> single driver/contribution and some number of receivers.  If you make
> wreal  different from a normal wire you create an artificial 
> distinction
> that just causes problems.
> 
> The "real" part of wreal is the type of the driver or receiver: wires
> (and ports) are just connectivity and have no type, only drivers and
> receivers have a type. Types are only associated with ports and wires
> because receivers and drivers are implicit constructs and cannot be
> directly annotated.
> 
> There is no particular reason that you can't just assign voltages and
> read them in digital processes the same way you do in analog 
> processes.
> In which case wreal can just be a synonym for a default 
> discipline wire.
> 
> Kev.
> 
> 
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