Verilog-AMS meeting minutes - 3/4 Feb 2010

Attendees:
Marek Mierzwinksi, Tiburon
Dave Cronauer, Synopsys
Ian Wilson, Berkeley DA
Ken Bakalar, Mentor
Gordon, Mentor
Patrick O'Halloran, Tiburon
Scott Little, FSL
Graham Helwig, ASTC
Martin O'Leary, Cadence
Dave Miller, FSL
Sri Chandra, FSL

Minutes:
Discussion on P1800 requirements gathering
   - Verilog-AMS presentation can be combined with the one being done
for ASVA. Ken Bakalar from Mentor is planning to develop (& present) the
ASVA aspects
   - Currently the fine details of the SV-AMS integration requirements
are not clear; however for the purposes of this meeting it will be good
to state the higher level intent and goals. This will be more
presentable to the audience.
   - In terms of SV-AMS merger discussions, few different options were
discussed:
     o deep integration of the two languages at the syntax & semantic level
     o P1800 dot standard where extensions to SV are made in a separate
committee/standard
     o Minimal extensions to support Verilog-AMS connectivity from SV
   - Gordon from Mentor mentioned that the P1800 committee had just gone
through lot of pain in integration P1364 & P1800 and it was not easy
(even tho' they are supposed to be same). So the SV committee may not be
able to digest another deep level integration
   - Ken mentioned that the (semiconductor) industry should push (show
support) for SV-AMS integration at the meeting; FSL is already on board
and possibly Intel. The issue is, if its not addressed in committee
vendors still need to support customers and there might be varied
implementations.
   - All of the above will be captured in the Verilog-AMS presentation
going be done for the P1800 requirements gathering group and sent across
to Ken early next week from the AMS committee (Sri will put to-gether a
presentation).
   - Presentations need to be submitted to Karen before Feb 12th; intent
conveyed before Feb 10th. Karen & Martin might attend this meeting in
person from the AMS committee.

Discussion on Syntax comparison between P1800 (one of the earlier
drafts) and Verilog-AMS
   - Graham has worked on a spreadsheet that compares the two languages
at the syntax level. He has also highlighted what changes are required
on the AMS or the SV side to have a common grammar. This is just a first
pass.
   - Some of the BNF differences are more fundamental and might affect
the semantics on how SV and Verilog-AMS handle these constructs. There
is differences in primary, constant_primary, real etc that needs to be
reconciled during the integration
   - Currently Graham did not have keyword document of SV, but once he
gets hold of it, he will do similar comparison on keyword clashes.
   - The document is placed at:
http://www.eda-stds.org/verilog-ams/htmlpages/cdd.html

Regards,
Sri

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