wreal (again)

The mantiss issue is - http://www.verilog.org/mantis/view.php?id=2378
(the status is wrong)

The proposal is not to remove the syntax but to redefine the semantics,
something like:

1. treat wreal as a wire of default discipline
2. allow direct assignment of analog values in a digital context (using
access functions)
3. reading a wreal in a digital context gives you "potential(<wreal
signal>)"
3. treat assignments to wreal types the same as "potential(<wreal
signal>) = <value>"
4. "flow(<wreal signal>) = 0.0" works as a disconnect (driving Z)
5. "potential(<wreal signal>) = NaN" can be used for equivalent of X

No macro defs, no odd scoping, no need for special connect modules.

If there are only digital context drivers and receivers then it works
the same as before and there is no need to go through the "analog
kernel" in simulation.

Going forward wreal would be deprecated and users could just use
V(<wire>) in digital as in analog blocks.

IMO the issue of fancy resolution schemes should be tackled at the SV
committees along with user-defined type use on wires (e.g. Jonathon's RF
signal modeling).

Kev.

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