Verilog-AMS committee meeting - 5th March (wreal proposal discussion)

Date: 5th March 2010

Attendees:
Ken Bakalar, Mentor
Prabal Bhattacharya, Cadence
Kevin Cameron, Consultant
Sri Chandra, Freescale
Scott Cranston, Cadence
Dave Cronauer, Synopsys
Jonathan David, Qualcomm
Graham Helwig, ASTC
Marq Kole, NXP
Top Lertpanyavit, Intel
Marek Mierzwinski, Tiburon
Dave Miller, Freescale
Patrick O'Halloran, Tiburon
Martin O'Leary, Cadence
David Sherritt, Tiburon
Gord Vreugdenhil, Mentor
Kishore, Cadence
Pranav, ??

Minutes of the meeting:

(Note: If i have misrepresented any of the discussions please feel free
to add/correct).

Martin gave a presentation on the Cadence donation for extensions on wreal
   * the donation window was opened 2 weeks back during the meeting on
18th Feb for a period of one month.
   * this is a review of the technology donation from Cadence in order
to vote on its acceptance as a donation to the Accellera Verilog-AMS
standards as extension to current standard
   * this is not a vote on its inclusion into the actual standard; this
inclusion will be done as per the usual committee language development
process.
   * Request to upload the document in Accellera committee page. Martin
has sent it across and has been uploaded by Dave Miller (thanks!). This
proposal can be found at:

Queries regarding donation during the meeting
   * Query from Kevin on macro `wrealZstate? Why cant we just use 1`bZ.
These are just using the same way constants are defined. 1`bX has
conversion issues which might cause issues.
   * Ken inquired about the use model that the proposal is trying to
address and these just not mere syntax extension. His concern was that
the use model is not very clear.
     - Does not address the issue of interface connectivity between
wreal2logic
     - one of the use cases is wreal to replace electrical model for
faster simulation
   * Global scope of discipline (for resolutions to work)
     - what happens when there is clash of wreal discipline
   * The need for a new structure to resolve current outstanding open
issues was questioned. Is there a need for a new structure?
   * absdelta - conversion from continuous signal to a wreal signal
     - cant we use @cross in digital context? This defines implicitly
the sample rate.
     - this function can be useful to decide when to do the sampling, no
relationship with wreal feature, the useage is for converting any real
signal
   * Top from Intel raised the issue of using real valued ports within
SystemVerilog
     - the current real valued ports is not treated as a "net" and does
not have the same semantics
   * Kevin raised his proposal for deprecating wreal - just using analog
type and use discrete drivers and receivers

Voting on the donation:
   * Expect members to send the response in 2 weeks time; March 18th
   * Requested all members/attendees to provide feeback/comments,
however only members of Accellera can vote on the proposal donation.
   * Sent email to technical committee chair (Sri) and also Cc Accellera
chair (Karen Pieper <karen_l_pieper@yahoo.com>)

Regards,
Sri

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