The deprecation proposal that has been floating around in Mantiss is for
the semantics of the current wreal not the syntax - the proposed change
would not invalidate any existing code.
Deprecation is not removal, it is the step before that where the
functionality is supported but not recommended. I.e. going forward the
recommend methodology would be to just use regular wires/disciplines and
use V(<wire>) = <value> (in a digital context) rather than using the
distinct wreal type. It will be clearer in the code what the intent is,
e.g. if the wreal (as was) is the voltage level out of a power
management block: "V(power_out) = 0.0" is easier to verify than
"v_power_out = 0.0".
The Mantiss proposal is simpler since it does not involve
connect-modules to achieve plug-and-play.
If you want to add resolved types with real values I would suggest using
different names for the types e.g.: wreal_r. If you do that then it is
easier to migrate to using a typedef'd version later in
SystemVerilog(-AMS) than it is to deal with the macro-def approach.
I would recommend voting "no" on accepting the Cadence proposal since
lacks technical merit: increased complexity, untidy syntax and lack of
forward compatibility.
The Mantiss proposal has no associated patents.
Kev.
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