RE: addition for wreal discussion

Hi Sri,

Dave Miller tells me that the paper "ADMS_Signals: Nets of User-defined
Type in Standard SystemVerilog

for Event-driven Analog Modeling" should appear on the website before
the end of the day.

Let me begin by saying that Mentor has no objection to accepting the
CDNS donation for consideration by the committee. We need to arrive at a
consensus on what Verilog-AMS is going to look like in the future so
that we can avoid a welter of proprietary extensions. All disclosures
are welcome. In that spirit, we disclose an alternative idea.

Sri calls ADMS_signals the "VHDL approach" even though it is coded in
standard SystemVerilog. A similar modeling style is available in
SystemC, and it provides all of the functionality of the Qualcomm
Verilog/VPI-based extension. He is correct in assuming that it supports
analog modeling methodologies that has been used successfully for years
in VHDL shops. I offer ADMS_signals not as a finished solution (there
is no A-D boundary) but to open up the discussion.

The prefix "ADMS" is an acronym for "analog, digital, mixed-signal", by
analogy with "AMS": "analog, mixed-signal". The resemblance to the name
of an existing product is purely coincidental :-). Mentor does not claim
"ADMS" as a trademark.

Our concern is that sophisticated users of event-driven analog modeling
have demonstrated a need for a more open-ended solution than the one
offered by the CDNS proposal. I do not call the required solution "real
number" modeling, since that assumes the consequent--that a single real
number is an adequate data representation.

Qualcomm discussed the limitations of the CDNS implementation in the
P1800 meeting. There are numerous papers in the open literature that
talk about the need for composite types in RF baseband modeling and
other areas. I know of semiconductor design shops that have created
remarkably clever (and up to this point, proprietary) analog
event-driven modeling styles that require a composite data type with
custom resolution rather than a single real number with a small, fixed
set of resolution options. CDNS has offered assurances without evidence
that their customers are happy with their solution. Let's hear from
their customers in a concrete way before we jump on this.

The addition of an intricate system of automatic boundary insertion
paralleling electrical/logic boundaries does not hide the fundamental
limitation of the CDNS approach. Even without consideration of the need
for composite data types, the boundary insertion mechanism violates a
fundamental design requirement of Verilog-AMS: it does not support
transparent replacement of a model in one format (electrical or logic)
with another (wreal). The argument offered by some that we can "fix that
later" is weak. Let's get the specification right now.

Best Regards,

Ken

-----Original Message-----
From: Sri Chandra [mailto:sri.chandra@freescale.com]
Sent: Monday, March 22, 2010 12:39 AM
To: Bakalar, Kenneth
Cc: Dave Miller; Chandrasekaran Srikanth-A12788
Subject: Re: addition for wreal discussion

Ken,

I have cc'ied David Miller who will upload the document on to the

Verilog-AMS web page. I am not sure whether he is the "webmaster" but as

you would have seen from reflector emails he does most of the uploading

of documents. I assumed that you had sent this to the reflector but you

just sent to owner-verilog-ams. I got this email at 2.17am my time on

Saturday, so i guess this was some time in the afternoon in US on

Friday, which is before the deadline.

I just had a brief look at this document. This details the ADMS/VHDL

approach for solving real number modeling (at a brief glance at the

documentation that you have sent). Just to make sure I understand

correctly, are you proposing this methodology as a parallel

(complimentary?) approach to what is being proposed today by Cadence and

for the committee to consider this proposal also for dealing with

handling of real number modeling?

Regards,

Sri

On 3/20/2010 2:17 AM, Bakalar, Kenneth wrote:

> Hello whoever is webmaster these days,

>

> I would like to post this document to

> http://www.eda-stds.org/verilog-ams/htmlpages/cdd.html as a
contribution

> to the discussion on "real number" modeling, within the contribution

> window that closes today (just to avoid any potential
misunderstanding).

>

> Let me know if this works. Once it is up I will write a cover letter
to

> the Verilog-AMS Reflector (verilog-ams@eda.org

> <mailto:verilog-ams@eda.org>) with the URL.

>

> Best Regards,

>

> Ken

>

>

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