Verilog-AMS technical committee meeting - 1st April 2010

From: Sri Chandra <sri.chandra@freescale.com>
Date: Wed Mar 31 2010 - 07:31:00 PDT

Hi all,

Firstly, the voting timeline for the cadence wreal donation closed on
19th of March. I am awaiting confirmation on couple of items from Karen
Pieper (Accellera chair) before i publish the result.

For the next call we will have a discussion on the proposal that Ken
Bakalar has sent across complimentary to the current discussion on wreal
(additions to the wreal discussion). Ken - I am hoping you will be able
to go through this during the upcoming call. If this time/date is not
convenient let me know and we might have to postpone it to next week.
The Cadence proposal has already been loaded in the Verilog-AMS webpage
and can be found at:

http://www.eda-stds.org/verilog-ams/htmlpages/cdd.html

Direct link to doc can be found at:
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/ResolvedCompositeSignalsInSVv4.pdf

(I am not available this week, but David has agreed to open the
conference call and proceed with the meeting).

Regards,
Sri

Details of the call are below:
Date: 1st April 2010

Call-In Details:
USA Toll Free : 8008671147
Australia Toll Free: 1800009128
India Toll Free : 0008006501482
Netherlands : 08002658223
Passcode: 0970751#

California: 2.00p (Thursday)
Texas: 4.00p
New York: 5.00p
Netherlands: 10.00p
Israel: 11.00p
Delhi: 2.30a (Friday)
South Australia: 7.30a

Note: This week also the meeting will be held on Thursday afternoon in
the US.

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Received on Wed Mar 31 07:31:34 2010

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