Re: Question on the domain of a variable

Since it's a mixed signal language and most things in Verilog are
globally accessible, your "x" doesn't really have a domain (and probably
shouldn't). IMO you should be able read or write to it from analog and
digital contexts (it's just a question of when that happens).

The LRM dates back to when there were a large number restrictions on
behavior because of the existing implementations, but a rule I try to
maintain as we move forward is that if you move a declaration around it
shouldn't change the behavior i.e.: if you moved the "real r" into the
analog block and used an <analog block>.r reference instead that
shouldn't change the behavior.

Kev.

On 05/06/2010 05:53 AM, Luc Rebillard wrote:
> Hello,
>
> According to the LRM, the domain of a variable (integer, real) is
> determinated by the context in which this variable
> is assigned. This recalled, I wonder what is the domain of the
> variable 'x' is the following module
>
> module test ;
>
> real x = 1.0 ;
>
> analog @(initial_step) $display("x=%f",x) ;
>
> initial $display("x=%f",x) ;
>
> endmodule
>
> Thanks,
>
> Regards,
>
> Luc
>

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