Re: Port directions

In Ken's earlier message, he was talking about signal-flow disciplines,
eg "discipline voltage" in the LRM. I expect those dummy loads would
use "electrical" (a conservative discipline) in which case you both agree
that input/output has no meaning.

I've never worked with signal-flow disciplines, but I don't imagine
that back-annotation is ever used with them.

-Geoffrey

Kevin Cameron wrote:
> From a circuit designers perspective source/sink is an aspect of
> function not current sign. E.g. on accelerometer circuits we had at
> Ferranti there were constant-current sinks used as dummy loads, I don't
> think input/output has any meaning in that context.
>
> Kev.
>
> On 06/04/2010 12:05 AM, Ken Kundert wrote:
>> It would be an input if you are sensing the current, and an output if
>> you are driving the current. Sourcing or sinking is just an issue of the
>> sign of the current.
>>
>> -Ken
>>
>> On 06/03/2010 11:40 PM, Kevin Cameron wrote:
>>
>>> I don't think that's sufficient - is a constant current a source or a
>>> sink, input or output?
>>>
>>> The input/output stuff makes sense at some levels of abstraction, but
>>> not when you're talking about which way currents are going. You would
>>> also have to consider the interaction with sub-modules, OOMRs and
>>> back-annotation.
>>>
>>> I think any attempt interpret input/output usage as an error will just
>>> cause problems. I voted "no" on this one when it came up for Verilog-A
>>> 1.0, I'm still voting "no".
>>>
>>> I would suggest talking to your vendor(s) and getting it added as an
>>> option to see how it works in practice before committing anything to the
>>> LRM.
>>>
>>> Kev.
>>>
>>> On 06/03/2010 05:49 PM, Ken Kundert wrote:
>>>
>>>> Marq,
>>>> It seems to me that with signal flow the port direction can be
>>>> checked to assure that it consistent with the behavior.
>>>>
>>>> Kevin,
>>>> Signal flow is easily recognized by the fact that the disciplines
>>>> have only one nature.
>>>>
>>>> -Ken
>>>>
>>>> On 06/03/2010 05:26 PM, Kevin Cameron wrote:
>>>>
>>>>
>>>>> How are you going to recognize signal flow?
>>>>>
>>>>> You might want to try addressing this issue in the assertions committee
>>>>> - i.e. if you can make up some rule about
>>>>> drivers/contributions/disciplines that can be tested then this problem
>>>>> moves into user space (being programmable) rather than being
>>>>> hard-defined in the standard.
>>>>>
>>>>> Kev.
>>>>>
>>>>> On 06/03/2010 02:26 AM, Marq Kole wrote:
>>>>>
>>>>>
>>>>>> Hi Kevin, Ken,
>>>>>>
>>>>>> I can understand not wanting to impose this limitation for conservative disciplines, but how about signal-flow disciplines? There you want to make sure that not more than one driver exists for a potential-only discipline or more than one sink for a flow-only discipline.
>>>>>>
>>>>>> Cheers,
>>>>>> Marq
>>>>>>
>>>>>> -----Original Message-----
>>>>>> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of David Miller
>>>>>> Sent: Wednesday 2 June 2010 21:01
>>>>>> To: Verilog-AMS LRM Committee
>>>>>> Subject: Port directions
>>>>>>
>>>>>> Should the language enforce that port directions are honored?
>>>>>> Specifically ports that are defined as input, should it be a error if you
>>>>>> contribute to a branch containing that port?
>>>>>>
>>>>>> module mymod(a,b);
>>>>>> electrical a,b;
>>>>>> input a,b;
>>>>>> analog V(a,b) <+ 5;
>>>>>> endmodule
>>>>>>
>>>>>> Should this be an error, since a,b are input?
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>
>>
>
>

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