RE: 0003177: Real numbers with scale factors in digital delays

You need to add parentheses to these lines:

> tb1 tut1;
> tb2 tut2;

to be

> tb1 tut1();
> tb2 tut2();

Module declarations don't require parentheses if they don't have port lists, but module instantiations do.

Regards,
Shalom

> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
> Behalf Of Marq Kole
> Sent: Monday, August 09, 2010 12:23 PM
> To: verilog-AMS LRM Committee
> Subject: RE: 0003177: Real numbers with scale factors in digital delays
>
> Hi Shalom,
>
> On your last remark - this would imply a default timescale directive -
> 1364-2005 (19.8, p.358) says that is simulator-specific and does not
> even offer a suggestion. I do agree that most users would apply a
> `timescale 1ns/1ps but that's not something to build a standard on.
>
> Simple test case:
>
> `timescale 1ns/1ps
>
> module test1 (output out, input in);
> assign #10ns out = in;
> endmodule // test1
>
> `timescale 10ns/1ps
>
> module test2 (output out, input in);
> assign #10ns out = in;
> endmodule // test2
>
> `timescale 1ns/1ps
>
> module tb1;
>
> reg in;
>
> initial
> in = 0;
>
> always
> #20 in = ~in;
>
> test1 mut1 (out1, in);
> test2 mut2 (out2, in);
>
> endmodule // tb1
>
> `timescale 10ns/1ps
>
> module tb2;
>
> reg in;
>
> initial
> in = 0;
>
> always
> #2 in = ~in;
>
> test1 mut1 (out1, in);
> test2 mut2 (out2, in);
>
> endmodule // tb2
>
> `timescale 1ns/1ps
>
> module test_timescale_time_value_tb;
>
> tb1 tut1;
> tb2 tut2;
>
> initial
> #1000 $finish;
>
> endmodule // test_timescale_time_value_tb
>
> Unfortunately, my Verilog compiler does not seem to allow time values
> in a delay - it "expects" another token than the 'ns' found here. As
> far as I can tell the above code is SV compliant ...
>
> Perhaps somebody wants to try this and tell me the results (or tell
> what I need to change in the test case without removing the time values
> from the delays).
>
> Marq

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