RE: Verilog-AMS committee meeting minutes - 11 Aug 2010

Hi,

I will be on vacation from Aug 23-30, so I won't attend the Aug 25 call.
But I am willing to work with Graham off-line, if he wishes, either by email or by phone.

Regards,
Shalom

> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
> Behalf Of David Miller
> Sent: Tuesday, August 17, 2010 10:24 AM
> To: Verilog-AMS LRM Committee
> Subject: Verilog-AMS committee meeting minutes - 11 Aug 2010
>
> Attendees
> Graham Helwig
> Shalom Bresticker
> Ian Wilson
> Achim Bauer
> Dave Cronauer
> Sri Chandra
> Dave Miller
>
> Purpose of this meeting was to begin the review of the initial grammar
> changes
> Graham has done to merge Verilog-AMS and SV.
>
> A comment was raised on the reflector questioning whether we should be
> focused
> on what will be needed to get the SV committee to incorporate our
> changes.
> Sri pointed out that we will be putting forward this work as a dot
> standard,
> and that this SV committee has already agreed that this work needs to
> be done.
>
> Specific points regarding the grammar document:
> * At the moment the merging points are fairly well defined but any
> conflicts
> especially in things like keywords will need to be resolved asap.
> * Currently the analog function declaration has been limited to the
> module
> scope. Question was raised whether they should be at the same location
> as a
> digital function declaration.
> * Also question why we have the restrictions on not allowing digital
> user
> defined functions to be called from within analog scope. This
> restriction can
> be inconvenient at times, especially when you have a common function
> that you
> may want to call from analog or digital.
>
> * Because we may end up placing certain analog constructs within the
> large SV
> items like packages, we need to ensure that we note where any semantic
> restrictions will be needed.
> * All of these restrictions should be raised in an Mantis item to
> enable tracking.
> * We should also capture any features / changes that are made that will
> not be
> backward compatible. It was mentioned that it would be a good idea if
> the new
> merged grammar did *not* contain optional syntax purely to support
> backwards
> compatibility. Tools and implementations can be backwards compatible,
> not the
> language.
>
> * Graham to investigate if branch_declaration can be added to the
> package item
> (at the same location where nodes are defined).
>
> * Same situation as alias parameters. Should they move into the
> package item.
> They may however only make sense at the module scope. We need more
> understanding of how exactly packages can be used.
>
> * Also with natures and disciplines. These seem, at first glance, to
> fit in
> well with the package methodology.
> * Remove the optional ';' character from the nature and discipline
> definition
> and make it mandatory to fit in with similar SV features.
>
> * Paramsets use a integer and real declaration type. However in System
> Verilog
> the integer and real declarations have had significant changes. Graham
> to
> investigate whether we can use the new types or if we need a separate
> type just
> for paramsets (and anywhere else integer and real declarations are used
> specific to analog.
>
> * Questioned whether discipline_identifier should be moved into the
> net_port_type item. It would make the most sense, but may cause
> unwanted side
> effects that semantic restrictions can cleanly resolve.
>
> * Stopped at type declarations.
>
> * Question was raised by Achim, whether we should be able to have
> access to the
> SV standard (1800-2009). Previously it was mentioned that we may get
> free
> access to that document for standards work. Sri to follow up.
>
> * David to post updated grammar document to the web (done)
>
> Next meeting will be 25th August 2010
>
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>
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