Re: Verilog-AMS committee meeting minutes - 8 Sept 2010 - reg/disc/wreal

On 09/09/2010 07:58 AM, David Miller wrote:
> * Discussions on real and reg declarations
>
> * The concept of a reg has become obsolete in SV and are nothing
> more than a variable..
> * They are not specific net types and hence these declarations are
> not found in the grammar.
>

Not really -

http://www.eda-stds.org/sv-dc/hm/0058.html

- the concept isn't dead only the requirement for explicit declaration,
and that causes some problems when you get into using user defined types
and code analysis.

> * How about discipline identifiers in port declaration. Should it be
> handled as part of net_port_type?
>
> * can this be pushed down rather than appear in top level syntax -
> how and where?
> - data or net declaration; not a simple issue to add this
> * configuration? sv-dc is not looking at disciplines currently.
> This is not part of the requirements list. Achim was wondering
> whether this should be raised within SV-DC committee
> o Scott mentioned that its likely sv-dc committee may not
> look at disciplines
> o this capability is required for enabling multi-power
> supplies. Now this information is back annotated
>

It has been raised because you need to get nominal supply voltages from
somewhere and it's easier/better to get them from the disciplines than
to try feeding them down the hierarchy as parameters or hard coding them
in models - i.e. you really want to be looking at the resolved
discipline of a net for that info (in the absence of a power supply
connection), particularly in connect modules.

I'd suggest confining discussions on wreal to the SV-DC committee to
avoid unnecessry duplication of effort and confusion.

Kev.

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