RE: SVA assertion of "analog" reals

Hi Achim,

The interpolation you refer to will never be a cubic spline. This interpolation is required to be a linear interpolation - a cubic spline would "generate" information that is not present even if the interpolated signal was continuous.

For the rest I think your interpretation is correct: there is no issue if the measurement done in the body of the timer event is the last value assigned to the real variable used to store the measurement result.

As a general rule: interpolation only happens if there are at least two points: one later and one earlier. When the later point is absent interpolation is not performed as it would actually be extrapolation. Using the last value assigned is then a reasonable choice.

Cheers,
Marq

Marq Kole
Product Manager AMSRF Simulation
NXP Semiconductors / Central R&D / Foundation Technology

From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Achim Bauer
Sent: Friday 19 November 2010 11:31
To: verilog-ams@eda.org; asva@lists.accellera.org
Subject: SVA assertion of "analog" reals

Hi,

following I send you a short description of the SVA assertion scenario, that I mentioned in the last Verilog-AMS meeting.
I did not code it, because i.m.h.o that would not really help you to grasp the case.

Suppose you want to measure and assert something very accurately, lets say power consumption. In such a case you might accomplish the measurement on the analog side, e.g. by using @(timer()...); so you are able to schedule and process an appropriate number of samples and you can take into account the precise "analog" time steps.

Now imagine the following scenario: we have a digital sampling signal "sample". Somewhere after @(posedge sample) the analog side shall start to measure power consumption and well before @(negedge sample) the timer "process" shall have completed its measurement; the offset or the period of the timer shall temporarily be set to infinite (i.e. 1Gs) so that the real-valued measurement result is savely kept.

With @(negedge sample) an SVA assertion on the digital side shall fetch this measured power value. It shall assert e.g. if a certain threshold is not exceeded depending on the circuits state / power control settings. If the assertion receives a value, that has been interpolated (e.g. via a cubic spline), the measurement might be falsified and the assertion might not work properly.

Verilog-AMS2.3 / 7.3.3 states clearly:
"If the current time in the continuous and discrete kernels differ, interpolation is used to determine the value to be used in the discrete context for the continuous variable UNLESS the value of the continuous variable was last assigned in an analog event statement. In this case, the value used in the digital context is exactly the same as the last value assigned to the continuous variable."

If I do not misunderstand this, in that real-value scenario the assertion should receive the last value that has been assigned within the timer block, but NOT an interpolated one. In the ASVA committee we talked a lot about interpolation for analog assertions and so I was not quite sure, if everybody was aware of this aspect.

Best regards,
                    Achim

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