RE: Cross examples

Hi Paul,

Indeed, these examples are wrong - they should be fixed in the way you suggest.

Cheers,
Marq

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Paul Floyd
Sent: Tuesday, February 01, 2011 3:53 PM
To: verilog-ams@eda.org
Subject: Cross examples

Hi

In 5.10.3.1, both of the examples for cross have

parameter integer dir = +1 from [-1:0] exclude 0;

I think that ought to be "from [-1:1] exclude 0", to allow choosing
negative and positive going edges for the sampling clock. As it stands
the examples must be instantiated with 'dir' set to -1.

Regards
Paul Floyd

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Dr Paul Floyd
Mentor Graphics Corporation
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