RE: Scope of 'ground' discipline

Dave,
Since each of these items that Paul has brought up are different errors should there be multiple Mantis items to capture them?
Regards
David

David W. Smith
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-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Dave Miller
Sent: Thursday, February 03, 2011 6:55 AM
To: Paul Floyd
Cc: verilog-ams@eda.org
Subject: Re: Scope of 'ground' discipline

Hi Paul,
I believe the example of sigmadelta is incomplete. The net discipline declaration should be at the same scope. So the example in sigmadelta should be:

electrical gnd;
ground gnd;

I will raise a single Mantis item to capture all these errors you have reported over the last few days.

Cheers...
Dave

On 02/03/2011 08:16 AM, Paul Floyd wrote:
> Hi
>
> In this paragraph
>
> "3.6.4 Ground declaration
> Each ground declaration is associated with an already declared net of
> continuous discipline. The node associated with the net will be the
> global reference node in the circuit. The net must be assigned a
> continuous discipline to be declared ground."
>
> ground declarations have to be associated with continuous disciplines.
> It doesn't explicitly state whether the association need be done at
> the same scope as the ground declaration or not. In the example below
> (from 6.2.2), the association for ground in module sigmadelta is done
> in the instantation C2 of comparator, which to me implies that the
> association need not be at the same scope.
>
> Do you think that it should be explicitly stated in the LRM that the
> scope of the association can be different? Alternatively, if the scope
> of the association should be the same as the gound declaration, there
> is an error in the example below.
>
> module comparator(cout, inp, inm);
> output cout;
> input inp, inm;
> electrical cout, inp, inm;
> parameter real td = 1n, tr = 1n, tf = 1n; real vcout;
>
> analog begin
> @(cross(V(inp) - V(inm), 0))
> vcout = ((V(inp) > V(inm)) ? 1 : 0);
> V(cout) <+ transition(vcout, td, tr, tf); end endmodule
>
> module integrator(out, in);
> output out;
> input in;
> electrical in, out;
> parameter real gain = 1.0;
> parameter real ic = 0.0;
>
> analog begin
> V(out) <+ gain*idt(V(in), ic);
> end
> endmodule
>
> module sigmadelta(out, aref, in);
> output out;
> input aref, in;
> ground gnd;
> comparator C1(.cout(aa0), .inp(in), .inm(aa2)); integrator #(1.0)
> I1(.out(aa1), .in(aa0)); comparator C2(out, aa1, gnd); d2a
> #(.width(1)) D1(aa2, aref, out); // a D/A converter endmodule
>
>
> Regards
> Paul Floyd

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