Verilog-AMS Committee Meeting Minutes - 4th Feb 2011

Meeting - Friday 4th February 2011

Attendees:
Sri Chandra (Freescale)
Dave Cronaur (Synopsys)
Ian Wilson (BDA )
Graham Helwig (ASTC
Achim Bauer (EXL Modeling)
Scott Little (Freescale)
Kevin Cameron (Consultant)
Martin O'Leary (Cadence)
David Miller (Freescale)

* Call times and meeting frequency
We will continue to meet fortnightly for the time being. Once some progress on
the document merge has been made, we can re-evaluate this to see if weekly
meetings might be more helpful with the reviews.

Call times will remain Thursday 1:30pm Central US Time. We will re-evaluate
these times once daylight saving changes come into effect in March.

* Update on open action items regarding P1800 document.

Sri meet with some representatives from P1800 during the week to discuss among
other things how we will go about managing documents.

At the very least we would like the style sheet for the P1800 document just so
what we work on has the same format, fonts layout etc. Ideally we would like
the frame source of the entire document as this would allow us to insert our
changes directly in place. If it meant that we had to put into place some sort
of access control to only nominated individuals, that would be fine.

We are still undecided how the final document will be, but at this stage,
developing the content of the document is more important then how it will look.

A comment from the meeting Sri had was how will the grammar be presented? We
would like to maintain a combined grammar (Appendix A) in a similar fashion to
what we have with Verilog-AMS / 1364.

Kevin raised the point that we need to be careful that from now on, SV doesn't
add in features that may directly conflict with our work. The SV-DC working
group is an example, which is working on methods to allow real valued modeling
within System Verilog.

A lot of these uses naturally cross over into the analog domain.

This point was discussed at length, however as Scott indicated. The SV-DC will
present a proposal to SV in early April. The Verilog-AMS committee will have an
opportunity to go over that proposal prior to it being submitted to the SV
committee.
Once we have that proposal, we will have a better understanding of what impacts
it may introduce. At that time we can suggest alternatives so that the proposal
will satisfy both parties.

There is also a few people who participate in both SV-DC and Verilog-AMS
committees which will hopefully mean potential conflicts are identified early.

Sri will also request that P1800 tries to keep Verilog-AMS in mind when
introducing possibly conflicting constructs into the language, since it is most
likely that by the time we have a System Verilog-AMS ready, it will be against
P1800-2011 and not the current P1800-2009 version.

Once again, our best defense is to rely on people who attend and participate in
both the Verilog-AMS and System Verilog committees to keep us updated on these
sorts of changes.

Sri plans to raise these questions in the P1800 call scheduled for 10th Feb.

With the resolution of real valued nets being one of the potential areas of
conflict between SV-DC and Verilog-AMS, one of the ideas put forward is should
Verilog-AMS put together a preliminary proposal on how resolution for analog
signals should/could happen in the discrete (SV) domain and provide that to
SV-DC group to take on as input. We will look at doing this.

Achim raised a concern of what happens with voting rights if we eventually
become part of IEEE. Apparently there has been a change in how contributions to
the working groups can happen within IEEE. Since we are not part of IEEE at
this stage, this does not concern us, but is something that we need to keep in
mind if/when we move away from Accellera.

Achim has some proposals he would like to put forward to the group for
inclusion into Verilog-AMS. He will get the proposals together and send them
across, David will follow up with him.

The Verilog-AMS website has been moved to the eda.org TWiki
http://www.eda.org/twiki/bin/view.cgi/VerilogAMS

A page has been created
(http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/SVAMSSectionWork) that lists
all the sections in the existing Verilog-AMS document. 13 of those sections
still have no owner.

If you would like to own a particular section for migration, please put your
name forward.

The next call will be Thursday 17th February.

An agenda will be distributed two days prior to the call.

Dialin Details:
San Francisco, 11.30a
Austin, 1.30p
Boston, 2.30p
Amsterdam, 8.30p
Tel Aviv, 9.30p
New Delhi, 1a (next day)
Adelaide, 6a

Call-In Details:
USA Toll Free : 8008671147
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India Toll Free : 0008006501482
Netherlands : 08002658223
Passcode: 0970751#

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-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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