RE: Verilog-AMS Committe Call - 31st Mar 2011

Hi,

I might be able to attend tomorrow's meeting.

I looked at Chapter 1 a little.

Here are a few editorial comments:

1. It calls SV and SV-AMS an "HDL". However, while Verilog was indeed called an HDL, SV is called an HDVL, Hardware Design and Verification Language (or even more fully, a Hardware Design, Specification, and Verification Language).

2. In referencing IEEE standards, the "S" in "Std" should be upper-case, i.e., "IEEE Std 1800-2009".

3. SV-2009 is "IEEE Std 1800-2009", not "IEEE Std P1800-2009" (no "P").

4. The third paragraph describes SV as "based on the Accellera SystemVerilog 3.1a extensions" to Verilog. While historically true, the time has come in 2011 to stop referring to SV 3.1a, which was really just an intermediate stage on the way to the IEEE. It is somewhat like saying that Draft 7 is based on Draft 6. SV 3.1a is a historical artifact that should be forgotten. I still encounter papers being written that mention SV and then put a reference to SV 3.1a in the footnote, instead of referencing IEEE 1800-2005 or 2009.

5. In 1.2, the font of "analog" in "analog procedural block" is not consistent.

6. Section 1.4, item 3 says, "Blue characters are used to denote syntax productions that are SystemVerilog-AMS extensions to IEEE std 1364-2005 Verilog HDL syntax." I believe that should be "extensions to IEEE Std 1800-2009 SystemVerilog syntax".

7. Item 7 says, "If the name of any category starts with an italicized part, it is equivalent to the category name without the italicized part. The italicized part is intended to convey some semantic information. For example, msb_constant_expression and lsb_constant_expression are equivalent to constant_expression, and node_identifier is an identifier which is used to identify (declare or reference) a node."

That text is old. SV-2009 does not use that form of partly-italicized name. Instead, SV-200 says, "A <i>qualified term</i> in the syntax is a term such as <i>array_identifier</i> for which the "array" portion represents some semantic intent and the "identifier" term indicates that the qualified term reduces to the "identifier" term in the syntax. The syntax does not completely define the semantics of such qualified terms; for example while an identifier which would qualify semantically as an array_identifier is created by a declaration, such declaration forms are not explicitly described using <i>array_identifier</i> in the syntax."

Regards,
Shalom

> * review of Chapter 1 Introduction for SV-AMS merge. Document found
> at:
> http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/SVAMSSectionWork#1_Ver
> ilog_AMS_introduction

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