Re: Verilog-AMS Committee Call - 28th Apr 2011

[Doubt I'll make a 6:00am call.]

Gordon posted some examples - http://www.eda.org/sv-dc/hm/0311.html

The examples in general are confusing instantiation statements with routine calls. Instantiation is mostly about connecting wires properly, and not about a single data transfer (as in a routine call). As mentioned before: types on ports in a module primarily tell you the type of receivers in the module, secondly any drivers, and nothing about the net unless you add a discipline.

A rather worrying example is the automatic conversion of a logic '1' to 1.0 as a real. In an AMS context you would probably expect that case to be handled by an A2D connect module to give you Vdd rather than 1.0. I can see this causing problems crossing power domains. The inclusion of Verilog-AMS disciplines into SV would help solve that problem.

The proposal does not address how primitives will work or any back-annotation methodology.

Given that there is still only one standing proposal for how to do back-annotation for Verilog-AMS -

 http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/BackAnnotationProposal

- which is equally applicable to SystemVerilog, I would recommend any proposal for discrete analog types in SV should support that back-annotation scheme (unless someone can come up with a better one that works for both).

Resolution and type conversion functions should be definable outside of the driver/receiver types (nettypes), since they may need to be defined later in the design process when modules are reused in new contexts (as is done with the AMS connect rules).

Kev.

On 04/26/2011 11:22 AM, Dave Miller wrote:
> Hello all,
> We have a call scheduled for Thursday 28th Apr 2011.
>
> Agenda:
> * SV-DC proposal. People have had a couple weeks to go over the proposal. If there are any issues that people have identified that will impact the AMS merge with SV, now is the time to raise them. This will allow us to pass them on to SV-DC so they can take them into consideration before they go to the champions committee.
>
> * Verilog-AMS representation in the SV-DC. Sri will discuss what this means.

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