Verilog-AMS Committee Meeting Minutes - 28th Apr 2011

Meeting - Thursday 28th April 2011

Attendees:
============
Sri Chandra (Freescale)
Graham Helwig (ASTC)
Ian Wilson (BDA)
Shalom Bresticker (Intel)
Kevin Cameron (Consultant)
Scott Little (Freescale)
Martin O'Leary (Cadence)
Dave Miller (Freescale)

* Accellera representatives
There has been recent changes to IEEE standards groups restricting participation.

However there is provision for Accellera to nominate representatives, up to
three. These representatives will represent the Accellera Verilog-AMS committee
on the SV-DC working group.

It is important that these individuals represent Accellera and the Verilog-AMS
groups best interest and not their individual companies.

It is expected that we will only get one vote within these groups, so the three
individuals need to arrive at a united decision on relevant items prior to voting.

The additional expectation is that the Verilog-AMS group is represented in all
calls so at least one of the three needs to attend each call.

The three people that Sri will put forward to Karen is Kevin Cameron, Ian
Wilson, and Martin O'Leary.

* SV-DC proposal for user defined nets.
There has been some concern raised with the SV-DC proposal for user defined nets.

Kevin feels that some of the default rules will not allow the accurate modeling
of hardware, which should be a goal. For example, converting logic '1' to 1.0
instead of vdd which would be what a hardware engineer may expect.

We understand why SV-DC didn't want to tackle the introduction of Verilog-AMS
disciplines, their charter was always to work within the existing constructs of
the SV language. But the concern is will we be able to use this proposal as the
ground work for future AMS work.

Martin also questioned why they are not looking at adding a built in type to
handle all this, similar to the existing 'wreal' construct in Verilog-AMS.

The main issue is, are we able to extend in the future what they are
introducing. If we are able to extend the ideas to accommodate Verilog-AMS,
then we are ok. However if we have conflicts, or have to redesign the features,
then that would be a problem, better resolved before it becomes part of the SV
standard.

We have two main questions to put forward to the SV-DC working group
1. Is the proposed solution going to allow the accurate modeling of hardware or
is there an alternative (realistic) that would satisfy both working groups.

2. Do they plan to introduce a built in real net type.

(DAVE: Please let me know if these two questions don't accurately reflect our
concerns.)

We will forward these questions onto the SV-DC working group.

Next call scheduled for Thurs 12th May.

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