Hi Dave,
Upon reading the chapter 1 (first things first, I guess) of the 3.0.0_draftA I found that the changes as specified in Mantis item #2266 have never materialized in section 1.3.4 although the Mantis item is currently set to "Resolved". This is the part on signal-flow disciplines that in VAMS LRM 2.3.1 are no longer restricted to potential only but can be either flow or potential. I would suggest that we reopen this Mantis item and get these changes in to remove the ambiguity with the rest of the AMS standard doc.
Cheers,
Marq
-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Dave Miller
Sent: Wednesday, May 11, 2011 4:10 AM
To: Verilog-AMS LRM Committee
Subject: Verilog-AMS Committee Call - 12th May 2011
Hello all,
We have a call scheduled for Thursday 12th May 2011.
Agenda:
* Review of Chapter 2 - Lexical conventions. Document can be found at:
http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/SVAMSSectionWork#2_Lexical_conventions
* Update on Verilog-AMS representation in the SV-DC.
Call Time: (Thursday 01.00pm UTC):
San Francisco, Thurs 06.00a
Austin, 08.00a
Boston, 09.00a
Amsterdam, 03.00p
Tel Aviv, 04.00p
New Delhi, 06:30p
Adelaide, 10:30p
Call-In Details:
USA Toll Free : 8008671147
Australia Toll Free: 1800009128
India Toll Free : 0008006501482
Netherlands : 08002658223
Passcode: 0970751#
Cheers...
Dave
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