Re: Fwd: [sv-dc] Generic interconnect

Dave - thank you for forwarding this.

This proposal appears to me to have significant impact on the feasibility
of integrating SV with Verilog-AMS, since it must somehow interact with the
AMS elaboration and net partitioning process.

(On the other hand, the user-defined types part of the proposal seems to
me to be less of a problem; I am expecting that we will be able to find a
way to use the rich type and class mechanisms in SV to import disciplines
in some way).

Gordon places much emphasis on the port collapsing semantics of Verilog
to remove complexity from the Generic Interconnect proposal. It may be that
any port connection that would be regarded by AMS as a candidate for
net splitting/connect module insertion is not collapsible, thus not a
potential
conflict (but if that is true, doesn't that restrict the domain of
usefulness of
Generic Interconnect severely)?

It seems to me that there are two incompatible views of interconnect within
the Verilog-AMS community:
   a) (the 'physical view'): interconnect does not affect the types of
the drivers
       and/or loads on the net, and therefore should not be considered whe
       doing discipline resolution
   b) (the 'IP view'): disciplines and other attributes can be applied
to interconnect;
       when present, these plays a primary role in discipline resolution

Gordon's proposal probably has different implications depending on which of
the above views you hold.

We need to understand the potential impact of the proposal on the future
feasibility of a Verilog-AMS integration with SV.

--ian

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