Re: Errors in wreal BNF

Thanks for the comments Marq.

I had missed the symmetry of electrical and wreal and I'm probably not using all the terminology 100% correctly either.

From my reading of the BNF it appears the following is a valid wreal statement.

wreal [3:0] net [5:0];

I believe this would be called an array of vectored real nets, where the vector part to me looks a lot like a packed array of real nets (which I believe is illegal). Unlike a logical vector the individual elements(bits) in the real vector cannot be combined to represent a single value, so that is my confusion. Basically, what does wreal [3:0] net actually represent and how is it different than wreal net [3:0]?

My assumption is that wreal [3:0] net [5:0] may be equivalent to wreal net [5:0][3:0]. Except a vector of real nets would sidesteps the 1364 limitation that arrays cannot be passed.

Regards,

Cary

________________________________
From: Marq Kole <marq.kole@nxp.com>
To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Sent: Wednesday, September 28, 2011 12:09 AM
Subject: RE: Errors in wreal BNF

Hi Cary,
 
I think your assessment of the items below being errors is a bit premature: wreal simply follows the interface descriptions that are also used in electrical and logic. This is a necessary requirement for Verilog-AMS. Do remember that we have not yet merged with SV - any incompatibility needs to be resolved correctly in order to maintain the underlying modeling capabilities. The modeling capabilities that are necessary for real-valued models based on wreal is a consistency between the following declarations:
 
  inout [3:0]      cont_value_net;
  electrical [3:0] cont_value_net;
 
and
 
  inout [3:0]      cont_value_net;
  wreal [3:0]      cont_value_net;
 
As there are already a lot of models using wreal interfaces out there, we cannot simply declare the above constructs as illegal.
 
Also, your statement below under item 1 about arrays of wreal is not correct: wreal is a net specification, not a type specification. It is not automatically connected to a (packed) array of reals - that would require a separate declaration and continuous assignment.
 
I do agree that wreal is always signed so the "signed" qualifier would be superfluous. I'm not sure that this syntactic sugar does any harm. It might be a gentle reminder to the user that the value carried on such a net is signed.
 
Cheers,
Marq
 
 
-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Cary R.
Sent: Tuesday, September 27, 2011 1:26 AM
To: Verilog-AMS LRM Committee
Subject: Errors in wreal BNF
 
I noticed the following errors in the wreal BNF in the
2.3.1 specification. I believe these will still apply after
the merge with 1800-2009.
 
1. Page 42 Syntax 3-8 and page 330 A.2.1.3
 
Delete [range] from both lines.
 
 
wreal should not take a [range]. Arrays of wreal are
handled in the list_of_net_... part of the syntax. In SV
this range would imply a packed array, but a packed
array of reals is not valid.
 
2. Page 132 Syntax 6-7 and page 329 A.2.1.2
 
Make new lines (three) for wreal and delete the [signed]
and [range] fields for the new wreal lines.
 
A wreal (real value) is always signed and as was
described in 1 above, a range is not valid for a wreal.
 
Regards,
 
Cary
 
 

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