SV-AMS integration - ability to reuse existing Verilog-AMS IP

The main problem I encounter today is the inability to cleanly simulate a
design that contains a mixture of SystemVerilog / Verilog-AMS / Spice.
Specifically a top-level SV testbench that instantiates Verilog-AMS blocks
and/or spice subckts.

Would this be considered as a basic starting point / milestone for SV-AMS to
support?

What would I need in SV-AMS to be able to do this?
I guess interface elements are the first major item.
  * a continuous discipline (electrical)
  * connect modules / rules to handle the boundary conversions.

There is also support of the analog block, although that doesn't seem to be
that bad as long as we can cleanly identify what is analog, what is digital.

The other component to all this is the simulation cycle and where analog fits
in. I am not very familiar with how the simulation cycle for SV differs from
previous Verilog.

Anyone have any comments on whether this would be a good place to start? I am
trying to think of ways to break down the project into more manageable chunks,
but perhaps there are more fundamental elements we need to address that I am
missing.

Regards
Dave

-- 
==============================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
==============================================
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.