#	Title	Ranking 1 (HI)  2(MED)  3(LOW)	Approve  (Y / N)	Comments
1	Truncating vs Rounding when converting Analog to Digital times	1	N	Neither rounding nor truncating is correct. The best solution is to either except the number (exact match) or raise to the next time slice). This is to eliminate back tracking the digital simulator. It is also consistent with 1076.1
2	Driver-receiver Segregation	21		While it appears to be an extended form of signal resolution it is actually something quite different. The solution actually results in a partitioning of the net into multiple networks with different resolution schemes being used on different sections (analog net resolves using analog drivers with an analog value, digital net resolves using only the digital values).
3	A/D Convertor placement	10		This needs resolved.
4	Driver Type Function  (ENH)		N
5	A/D Synchronization	6
6	External Module Definitions  (ENH)	11		The problem is actually worse. If Verilog-AMS is meant to replace spice netlist then the issue stated is clearly a problem. Having a declaration mechanism (as suggested) does help to find the source. Unfortunately having the source is not enough. Each spice is different in its definition of the element parameters. A worse problem is the inability in Verilog-AMS to relate the process parameter information (model card) to any other system variables. While this is only a small problem with Verilog-2001 it will become significant when Verilog-plus-plus is released (next year). How much of a Spice netlist replacement is Verilog-AMS meant to be? I believe the Verilog 2001 syntax for include is: incluide <models.h>;  The 'include<models.h> seems inconsistent.
7	Back-Annotation  (ENH)		N
8	Mixed-signal language features
9	Genvars	12		Verilog 2001 compatability is important.
10	3.4.3.{2,3} Empty disciplines; undeclared nets
11	Ground declaration		N
12	Real net declarations
13	Default discipline	13
14	Restrictions on analog operators
15	Absolute delay operator		N
16	Analysis dependent functions		Y
17	Events	7		Key issue for portability and interoperability.
18	Global events
19	Top-level modules
20	Ports
21	Real valued ports	14		Also need to consider usage with respect to Verilog Plus Plus where there are many other types that can be used with ports.
22	8.2.{1,2} Domains. Contexts
23	Behavioral Interaction	2		Related to 1,5,17
24	Accessing discrete nets and variables
25	Concurrency	3		Related to 1,5,17,23
26	Discipline Resolution		N
27	Connection of continuous-time disciplines
28	8.{5-8} Connect Modules		N
29	Driver Access and net resolution		N	Agree with the "preferred" approach comment.
30	8.11 Supplementary driver access functions
31	9.2 Mixed-signal simulation cycle	4	Y	Related to 1,5,17,23,25
32	10 System tasks and functions	15	N	Look at Verilog 2001 plus Verilog Plus Plus for definition. They win.
33	Compiler directives
34	Standard definitions
35	SPICE compatibility
36	Discipline resolution methods
37	Coercion of strings to real allowed but not defined
38	When to do range checks?		Y
39	Connections to port expressions (whats a driver?)
40	OOMR disciplines on behavioral nets		Y
41	neutral disciplines
42	LRM cleanup issue: TRI and WIRE are aliases
43	Initial value of wreal nets not defined	8	Y	Initialization must be unambiguous.
44	Real value port examples have errors:		Y
45	default_discipline clarifications
46	default_discipline only for digital?
47	Discipline presendence issues
48	disiplines rules of branches
49	branches - clarifications
50	Initial Conditions
51	Implicit Switch Branches?		Y
52	Indirect assignments in conditionals		Y
53	Syntax consistencies with 1364	16	Y
54	(28) Syntax 6-3, Syntax 6-4, Syntax 6-5 and BNF		Y
55	Switch branches illegal in BNF		Y
56	defparam vs. instantiation precedence			Needs to be conformant to Verilog 2001.
57	Compatible disciplines		Y
58	Clarification on X and Z .
59	Discipline Resolution: No clear definition on how to deal with "leaf level" wires.		Y
60	Discipline Resolution: No clear definition on how to deal with out of module  references (OOMRs).		Y
61	bi-dir issues		Y
62	net_resolution function: No one liked this so if we are going to change it lets do it now.
63	Supplementary drivers and delays
64	Which solver starts first?	5		Related to 1,5,…
65	Initialization method - Different from VHDL	9	Y	Related to 1,5,…
66	1364 sync-up  Random function	17	Y
67	VPI Issue		Y
68	BNF clarification - Connectrules		Y
69	BNF clarification - Connectmodule		Y
70	flow and potential, should these be global keywords?			1364 wins
71	Annex C changes that were missed:  Null Argument
72	Annex C changes that were missed: Z-filter roots
73	Annex C changes that were missed:  boundstep argument
74	Annex C changes that were missed:  $random interpretation		Y
75	Discipline and Constants file corrections:		Y
76	Discipline and Constants file corrections:		Y
77	Discipline and Constants file corrections:		Y
78	Discipline and Constants file corrections:		Y
79	upcase issues with disciplines.vams file	18
80	SPICE master name conflict
81	Case sensitive SPICE simulators	19
82	Disciplines of analog primitives: How to set and defaults  (see 9_30)
83	Compatible disciplines to analog primitives  (see 9_9)
84a	LRM Cleanup Typos		Y
84b	LRM Cleanup Typos  II		Y
85	Support for global design variables (accessible throughout hierarchy)		N	Fix ambiguities elsewhere. Verilog Plus Plus is playing havoc with global variables. Look into this.
86	Issues on discipline and Nature compatibility
87	Issues on if-elseif	20
88	Issues with regards to example on Section 3.8
89	Add support for NaN & 'X'			Use Verilog 2001/Plus Plus as guide. What about inf etc… All IEEE floating point issues.
90	Discipline Compatibility		N	Focus on clarification and not enhancements
91	`include		N	Follow Verilog 2001 definition.
92	Mixed signal initialization (digital)
93	Filters for foreign languages		N	This is not a language issue but an environment issue. There are insufficient semantics to translate any spice netlist into Verilog-AMS. Filters are not possible without defining the missing semantics.
94	Light Weight Conversion		N	Minimize enhancements. Focus on clarity.
95	Representation Stops		N	This has little change of being adopted by the1364 committee or the IEEE standardization process.
			N	This has little change of being adopted by the1364 committee or the IEEE standardization process.
			N	This has little change of being adopted by the1364 committee or the IEEE standardization process.