Proposal for m factors in Verilog_ams

M factors are a method used in spice to allow instantiation
of multiple devices in parallel using only a single device.
They also apply to subckts (modules) where they apply to the 
contents of the subckt, including other subckts where the final
m factor of a primative is the product of all the m factors up
the instantiational hierarchy. M factors do not have to be integers.


In order to avoid conflicts with parameters called "m", 
an m factor is added to a Verilog instantiation as an attribute. 
Any instantiation in the module inv will inherit the m factor or multiply an m 
factor on an instantiation with one.
 
For example:
 
(* m_factor=3.0 *)
inv i0 (n1,n2);

module inv (n1,n2)

(* m_factor=3.0 *)
xx  i1 (n1,n2);
xx  i2 (n1,n2);
 
i1 will have an m factor 9 and i2 an m factor 3.
 
The m factors will automatically go to Spice elements.
 
For Verilog_ams contributions, I see two possibilities:
 
1. The user will have access to the m factor (say as m_factor Befault 1) in the
   analog block and make appropriate adjustments to the equations. It is then
   up to the module writer to apply the m factor appropriately, which is
   potentially error prone. It also means the m factor will apply to some
   modules and not to others.
2. The user will not have access to the m factor and the m factor will 
   automatically multiply all flow contributions by its value, divide the
   branch currents of all potential contributions and not effect signal flow.
 
For example:
 
I(n1,n2)<+ expr;   will return a current m_factor*I(n1,n2)
V(n2,n3)<+ expr;   will return a current through branch n2,n3 = I(n2,n3)/m_factor.