As of September 2004, the work on the Property Specification Language (PSL) has now moved from the Accellera Formal Verification Technical Committee, to the IEEE 1850 working group. Please visit www.eda.org/ieee-1850 for details.
The Accellera Formal Verification Technical Committee (FVTC) is chartered with developing and promoting a property specification language (PSL) compatible with both the Verilog (IEEE-1364) and VHDL (IEEE-1076) hardware description language standards. This formal language is targeted for both dynamic verification (e.g., simulation) as well as static verification (e.g., model checking).
The goal of this web site is to document and provide relevant information about ongoing activities related to the Accellera Formal Verification Technical Committee.
The Accellera PSL Version 1.1 LRM is available here.
For meeting details, select the meetings option in the left frame. For the latest status of the committee can be reviewed at here.
Chair: Harry Foster, Jasper Design
Automation.
Co-chair: Erich Marschner, Cadence.
Full committee membership list is no longer published on this website to protect the email addresses of the members from the spam spiders. Send email to the chair if you have any question.
Please send an email to majordomo@eda.org with the following in the body of the email:
subscribe vfv <email address>
FVTC mail reflector archive is located here.
Last
update on