IEEE 200X Fast Track Change Proposal

ID:	  FT-17

Proposer:     Jim Lewis 
email:        Jim@SynthWorks.com

Status:       Proposed
Proposed:     12/03
Analyzed:     Date
Resolved:     Date

Enhancement Summary:     Composite interface mode
Give VHDL the ability to specify the interface mode 
of an element of a composite object.  

Related issues:          FT-17
Relevant LRM section:    

Enhancement Detail:
----------------------------
Give VHDL the ability to specify the IO mode 
of an element of a record.  Useful for testbenches
and system modeling.

type IfRecType is record
  Sig1 : std_logic ;
  Sig2 : std_logic ;
  Sig3 : std_logic_vector(7 downto 0) ;
  Sig4 : std_logic_vector(7 downto 0) ;
end record ;


Mode IfRecType_Mode_Model1 : IfRecType := (
  Sig1 => in,
  Sig2 => out,
  Sig3 => inout, 
  Sig4 => in 
) ; 
Mode IfRecType_Mode_Model2 : IfRecType := (
  Sig1 => out,
  Sig2 => in,
  Sig3 => inout, 
  Sig4 => in 
) ; 


Entity Model1 is
port (
  IfRec1 : IfRecType_Model_Model1 : IfRecType ;
  . . .


Analysis:
----------------------------
[To be performed by the 200X Fast Track Working Group]


Resolution:
----------------------------
[To be performed by the 200X Fast Track Working Group]